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data sheet august 2001 orca ? ort8850 field-programmable system chip (fpsc) eight-channel x 850 mbits/s backplane transceiver introduction field-programmable system chips (fpscs) bring a whole new dimension to programmable logic: fpga logic and an embedded system solution on a single device. agere systems inc. has developed a solution for designers who need the many advantages of fpga-based design implementation, coupled with high-speed serial backplane data transfer. built on the series 4 reconfigurable embedded system-on-chips (soc) architecture, the ort8850 family is made up of backplane transceivers containing eight channels, each operating at up to 850 mbits/s (6.8 gbits/s when all eight channels are used) full-duplex synchronous interface, with built-in clock and data recovery (cdr) in standard-cell logic, along with up to 600k usable fpga system gates. the cdr circuitry is a macrocell available from agere?s smart silicon macro library, and has already been implemented in numerous applications including asics, standard products, and fpscs to create interfaces for sonet/sdh sts-3/ stm-1, sts-12/stm-4, sts-48/stm-16, and sts- 192/stm-64 applications. with the addition of protocol and access logic such as protocol-independent fram- ers, asynchronous transfer mode (atm) framers, packet-over-sonet (pos) interfaces, and framers for hdlc for internet protocol (ip), designers can build a configurable interface retaining proven backplane driver/receiver technology. designers can also use the device to drive high-speed data transfer across buses within a system that are not sonet/sdh based. for example, designers can build a 6.8 gbits/s pci-to-pci half bridge using our pci soft core. the ort8850 family offers a clockless high-speed interface for interdevice communication, on a board or across a backplane. the built-in clock recovery of the ort8850 allows for higher system performance, eas- ier-to-design clock domains in a multiboard system, and fewer signals on the backplane. network design- ers will benefit from the backplane transceiver as a network termination device. the backplane trans- ceiver offers sonet scrambling/descrambling of data and streamlined sonet framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary sys- tems. for non-sonet application, all sonet func- tionality is hidden from the user and no prior networking knowledge is required. the 8850 also offers 8b/10b coding in addition to sonet scram- bling. also included on the device are three full-duplex, high- speed parallel interfaces, consisting of 8-bit data, con- trol (such as start-of-cell), and clock. the interface delivers double data rate (ddr) data at rates up to 311 mhz (622 mbits/s per pin), and converts this data internal to the device into 32-bit wide data running at half rate on one clock edge. functions such as center- ing the transmit clock in the transmit data eye are done automatically by the interface. applications delivered by this interface include a parallel backplane interface similar to the recently proposed rapidio ? packet-based interface. table 1. orca ? ort8850 family?available fpga logic note: the embedded core and interface are not included in the above gate counts.the usable gate counts range from a logic-only g ate count to a gate count assuming 20% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pio groups are counted as 16 gates (three ffs, fast-capture latch, output logic, clk, and i/o buffers). pfus u sed as ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are used for each pll an d 50k gates for the embedded system bus and microprocessor interface logic. both the ebr and plls are conservatively utilized in the gate calculations. device pfu rows pfu columns total pfus fpga user i/o luts ebr blocks ebr bits (k) usable gates (k) ort8850l 26 24 624 296 4,992 8 74 260?470 ort8850h 46 44 2024 536 16,192 16 147 530?970
table of contents contents page contents page 2 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc introduction..................................................................1 embedded core features (serial)...............................4 embedded core features (parallel)............................4 programmable fpga features ...................................5 programmable logic system features .......................6 description...................................................................7 what is an fpsc? ...................................................7 fpsc overview .......................................................7 fpsc gate counting ...............................................7 fpga/embedded core interface .............................7 orca foundry development system .....................7 fpsc design kit ......................................................8 fpga logic overview ..............................................8 plc logic ................................................................8 programmable i/o ....................................................9 routing .....................................................................9 system-level features..............................................10 microprocessor interface .......................................10 system bus ............................................................10 phase-locked loops .............................................10 embedded block ram ...........................................10 configuration ..........................................................11 additional information ............................................11 ort8850 overview ...................................................12 device layout ........................................................12 backplane transceiver interface ...........................12 hsi interface ..........................................................15 stm macrocell .......................................................15 8b/10b encoder/decoder ......................................15 fpga interface ......................................................15 byte-wide parallel interface ..................................15 fpsc configuration ...............................................16 generic backplane transceiver application..............17 synchronous transfer mode (stm) .......................17 8b/10b mode .........................................................17 backplane transceiver core detailed description ....18 hsi macro ..............................................................18 stm transmitter (fpga ? backplane) .................20 stm receiver (backplane ? fpga) .....................23 8b/10b transmitter (fpga ? backplane) ............30 8b/10b receiver (backplane ? fpga) ................30 pointer mover block (backplane ? fpga) ...........31 receive bypass options and fpga interface .......33 powerdown mode ................................................. 33 stm redundancy and protection switching ......... 33 lvds protection switching ................................... 34 rapidio interface to pi-sched.................................. 34 overview ............................................................... 34 receive cell interface ........................................... 34 transmit cell interface .......................................... 36 memory map............................................................. 38 definition of register types .................................. 38 absolute maximum ratings...................................... 55 recommended operating conditions ...................... 55 power supply decoupling lc circuit........................ 56 hsi electrical and timing characteristics ................ 57 parallel rapidio -like interface timing characteristics......................................................... 58 embedded core lvds i/o ....................................... 59 lvds receiver buffer requirements .................... 60 input/output buffer measurement conditions (on-lvds buffer)..................................................... 61 lvds buffer characteristics..................................... 62 termination resistor ............................................. 62 lvds driver buffer capabilities ............................ 62 pin information ......................................................... 63 package pinouts ................................................... 77 package thermal characteristics summary .......... 105 ja ..................................................................... 105 jc ..................................................................... 105 jc ..................................................................... 105 jb ..................................................................... 105 fpsc maximum junction temperature .............. 105 package thermal characteristics........................... 106 package coplanarity .............................................. 106 package parasitics ................................................. 106 package outline diagrams..................................... 107 terms and definitions ......................................... 107 package outline drawings ..................................... 108 352-pin pbga ..................................................... 108 680-pin pbgam .................................................. 109 hardware ordering information .............................. 110 software ordering information ............................... 111
agere systems inc. 3 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc table of contents (continued) list of figures page list of tables page figure 1. . orca ort8850 block diagram .............13 figure 2. . high-level diagram of ort8850 transceiver ............................................................14 figure 3. . 8850 with 8b/10b coding/decoding ........18 figure 4. . hsi functional block diagram ................19 figure 5. . byte ordering of input/output interface in sts-12 mode .....................................................20 figure 6. . spe and c1j1 functionality ....................26 figure 7. . spe stuff bytes .......................................27 figure 8. . interconnect of streams for fifo ............28 figure 9. . example of inter-stm alignment ............28 figure 10. . example of intra-stm alignment ..........28 figure 11. . example of twin sts-12 stream ..........28 figure 12. . examples of link alignment ..................29 figure 13. . pointer mover state machine ................32 figure 14. . rapidio receive cell interface .............35 figure 15. . rapidio transmit cell interface ............36 figure 16. . sample power supply filter network for analog hsi power supply pins ........................56 figure 17. . receive parallel data/control timing ...58 figure 18. . transmit parallel data/control timing ..58 figure 19. . ac test loads ........................................61 figure 20. . output buffer delays .............................61 figure 21. . input buffer delays ................................61 figure 22. . lvds driver and receiver and associated internal components ...........................62 figure 23. . lvds driver and receiver ....................62 figure 24. . lvds driver ..........................................62 figure 25. . package parasitics ..............................106 table 1. . orca ort8850 family ? available fpga logic ................................................1 table 2. . transmitter toh on lvds output (transparent mode) .................................................22 table 3. . transmitter toh on lvds output (toh insert mode) ...................................................22 table 4. . receiver toh (output parallel bus) ...........25 table 5. . spe and c1j1 functionality .......................26 table 6. . valid special characters .............................30 table 7. . valid starting positions for an sts-mc .......31 table 8. . rapidio signals to/from fpga ...................37 table 9. . signals used as register bits ....................38 table 10. . structural register elements ...................39 table 11. . memory map .............................................40 table 12. . memory map descriptions .......................45 table 13. . absolute maximum ratings ......................55 table 14. . recommended operating conditions ......55 table 15. . absolute maximum ratings ......................57 table 16. . recommended operating conditions ......57 table 17. . receiver specifications ............................57 table 18. . transmitter specifications ........................57 table 19. . synthesizer specifications ........................57 table 20. . parallel receive data/control timing .......58 table 21. . transmit parallel data/control timing ......58 table 22. . driver dc data ...........................................59 table 23. . driver ac data ...........................................59 table 24. . driver power consumption .......................59 table 25. . receiver ac data ......................................60 table 26. . receiver power consumption ..................60 table 27. . receiver dc data ......................................60 table 28. . lvds operating parameters ....................60 table 29. . fpga common-function pin description ........................................................63 table 30. . fpsc function pin description ................66 table 31. . embedded core/fpga interface signal description ....................................................70 table 32. . ort8850h pins that are unused in ort8850l ...............................................................77 table 33. . ort8850l 352-pin pbga pinout .............78 table 34. . ort8850l and ort8850h 680-pin pbgam pinout ...........................................88 table 35. . orca ort8850 plastic package thermal guidelines ...............................................106 table 36. . orca ort8850 package parasitics .....106 table 37. . device type options ..............................110 table 38. . temperature options ..............................110 table 39. . package type options ........................... 110 table 40. . orca fpsc package matrix (speed grades) .....................................................110
4 4 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc embedded core features (serial) implemented in an orca series 4 fpga. allows wide range of applications for sonet net- work termination application as well as generic data moving for high-speed backplane data transfer. no knowledge of sonet/sdh needed in generic applications. simply supply data, 78 mhz ? 106 mhz clock, and a frame pulse. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without exter- nal clocks. eight-channel hsi function provides 850 mbits/s serial interface per channel for a total chip bandwidth of 6.8 gbits/s (full duplex). hsi function uses agere ? s 850 mbits/s serial inter- face core. rates from 212 mbits/s to 850 mbits/s are supported directly (lower rates directly supported through decimation and interpolation). lvds i/os compliant with eia ? -644 support hot insertion. all embedded lvds i/os include both input and output on-board termination to allow long-haul driving of backplanes. low-power 1.5 v hsi core. low-power lvds buffers. programmable sts-1, sts-3, and sts-12 framing. independent sts-1, sts-3, and sts-12 data streams per quad channels. 8:1 data multiplexing/demultiplexing for 106.25 mhz byte-wide data processing in fpga logic. on-chip, phase-lock loop (pll) clock meets b jitter tolerance specification of itu-t recommendation g.958. powerdown option of hsi receiver on a per-channel basis. selectable 8b/10b coder/decoder or sonet scram- bler/descrambler. hsi automatically recovers from loss-of-clock once its reference clock returns to normal operating state. frame alignment across multiple ort8850 devices for work/protect switching at oc-192/stm-64 and above rates. in-band management and configuration through transport overhead extraction/insertion. supports transparent modes where either the only insertion is a1/a2 framing bytes, or no bytes are inserted. streamlined pointer processor (pointer mover) for 8 khz frame alignment to system clocks. built-in boundry scan ( ieee ? 1149.1 jtag). fifos align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both sonet scrambling and 8b/10b modes. optional ability to bypass alignment fifos. 1 + 1 protection supports sts-12/sts-48 redun- dancy by either software or hardware control for pro- tection switching applications. sts-192 and above rates are supported through multiple devices. orca fpga soft intellectual property core support for a variety of applications. programmable stm pointer mover bypass mode. programmable stm framer bypass mode. programmable cdr bypass mode (clocked lvds high-speed interface). redundant outputs and multiplexed redundant inputs for cdr i/os allow for implementation of eight chan- nels with redundancy on a single device. embedded core features (parallel) three full-duplex, double data rate (ddr) i/o groups include 8-bit data, one control, and one clock. each interface is implemented with lvds i/os that include on-board termination to allow long-haul driving of backplanes, such as the industry-standard rapidio interface. external i/o speeds on ddr interface up to 311 mhz (622 mbits/s per pin), with internal, single- edge data transferred at 1/2 rate on a 32-bit bus plus control. automatic centering of transmit clock in data eye for ddr interface. direct interfaces to agere pi-sched (266 mhz ddr lvds), pi-x (128 mhz ttl), and apc (100 mhz ttl) atm/ip switch/port controller devices.
agere systems inc. 5 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc programmable fpga features high-performance platform design: ? 0.13 m 7-level metal technology. ? internal performance of >250 mhz. ? over 600k usable system gates. ? meets multiple i/o interface standards. ? 1.5 v operation (30% less power than 1.8 v oper- ation) translates to greater performance. traditional i/o selections: ? lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/ os. ? per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. ? individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. ? two slew rates supported (fast and slew-limited). ? fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. ? fast open-drain drive capability. ? capability to register 3-state enable signal. ? off-chip clock drive capability. ? two-input function generator in output path. new programmable high-speed i/o: ? single-ended: gtl, gtl+, pecl, sstl3/2 (class i & ii), hstl (class i, iii, iv), zbt, and ddr. ? double-ended: lvds, bused-lvds, lvpecl. ? lvds include optional on-chip termination resistor per i/o and on-chip reference generation. ? customer defined: ability to substitute arbitrary standard-cell i/o to meet fast-moving standards. new capability to (de)multiplex i/o signals: ? new ddr on both input and output at rates up to 133 mhz (266 mhz effective rate). ? new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-quad programmable function unit (pfu): ? eight 16-bit look-up tables (luts) per pfu. ? nine user registers per pfu, one following each lut, and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. ? new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. ? new lut structure allows flexible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. ? 32 x 4 ram per pfu, configurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ? soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing, which reduces rout- ing congestion and improves speed. ? flexible fast access to pfu inputs from routing. ? fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arith- metic functions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and efficient performance. slic provides eight 3-statable buffers, up to 10-bit decoder, and pal ? -like and-or-invert (aoi) in each programmable logic cell. improved built-in clock management with dual-output programmable phase-locked loops (pplls) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 mhz up to 416 mhz. new 200 mhz embedded quad-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be configured as: ? one ? 512 x 18 (quad-port, two read/two write) with optional built-in arbitration. ? one ? 256 x 36 (dual-port, one read/one write). ? one ? 1k x 9 (dual-port, one read/one write). ? two ? 512 x 9 (dual-port, one read/one write for each). ? two ram with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). ? supports joining of ram blocks. ? two 16 x 8-bit content addressable memory (cam) support. ? fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. ? constant multiply (8 x 16 or 16 x 8). ? dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit par- ity interconnects fpga logic, microprocessor inter- face (mpi), embedded ram blocks, and embedded backplane transceiver blocks with 100 mhz bus per- formance. included are built-in system registers that act as the control and status center for the device.
6 6 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc programmable fpga features (continued) built-in testability: ? full boundary scan ( ieee 1149.1 and draft 1149.2 jtag). ? programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ? ts_all testability function to 3-state all i/o pins. ? new temperature-sensing diode. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. this feature also enables compliance with many setup/hold and clock to out i/o specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. programmable logic system features pci local bus compliant for fpga i/os. improved powerpc ? 860 and powerpc ii high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga logic, rams, and embedded back- plane transceiver blocks. glueless interface to synchronous powerpc processors with user-config- urable address space provided. new embedded amba ? specification 2.0 ahb sys- tem bus ( arm ? processor) facilitates communica- tion among the microprocessor interface, configuration logic, embedded block ram, fpga logic, and backplane transceiver logic. new network plls meet itu-t g.811 specifications and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. flexible general-purpose pplls offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for or4e4). new local clock routing structures allow creation of localized clock trees. new edge clock routing supports at least six fast edge clocks per side of the device new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities inter- face high-speed external i/os to reduced speed internal logic. orca foundry 2000 development system software. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3. also meets proposed specifications for utopia level 4 for 10 gbits/s interfaces. two new edge clock routing structures allow up to seven high-speed clocks on each edge of the device for improved setup/hold and clock to out perfor- mance.
agere systems inc. 7 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc description what is an fpsc? fpscs, or field-programmable system chips, are devices that combine field-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the flexibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview agere ? s series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several col- umns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 effi- ciency, none of the fpga functionality is changed ? all of the series 4 fpga capability is retained: embedded block rams, mpi, pcms, boundary scan, etc. the col- umns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga func- tionality. the embedded cores can take many forms and gener- ally come from agere ? s asic libraries. other offerings allow customers to supply their own core functions for the creation of custom fpscs. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon-area efficient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core has been enhanced to allow for a greater number of interface signals than on previous fpsc achitectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the inter- face are precharacterized and accounted for in the orca foundry development system. series 4 based fpscs expand this interface by provid- ing a link between the embedded block and the multi- master 32-bit system bus in the fpga logic. this sys- tem bus allows the core easy access to many of the fpga logic functions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system flexibility, fpga configuration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality sim- ply by reconfiguring the device. orca foundry development system the orca foundry development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture, and then place and route it using orca foundry ? s timing-driven tools. the development sys- tem also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simula- tion, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: design entry and the bitstream gen- eration stage. recent improvements in orca foundry allow the user to provide timing requirement informa- tion through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation.
8 8 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc description (continued) following design entry, the development system ? s map, place, and route tools translate the netlist into a routed fpga. a floorplanner is available for layout feedback and control. a static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation and timing. timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram, embedded block ram, and/or fpsc memory. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with orca foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc configuration manager, synopsys smart model ? , and complete online documentation. the kit's software cou- ples with orca foundry, providing a seamless fpsc design environment. more information can be obtained by visiting the orca website or contacting a local sales office, both listed on the last page of this docu- ment. fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from agere. it includes enhancements and innovations geared toward today ? s high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a vari- ety of packages and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gration with true plug-and-play design implementation. the architecture consists of four basic elements: pro- grammable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), and system- level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs are surrounded by common interface blocks which provide an abundant interface to the adja- cent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the pro- grammable logic core. each plc contains a pfu, slic, local routing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pal -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex- ing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 quad- port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic func- tions. the pfu is organized in a twin-quad fashion; two sets of four luts and ffs that can be controlled indepen- dently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic func- tions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset.
agere systems inc. 9 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc description (continued) the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3- state, bidirectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pal -like functions. the 3- state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real-world system performance. programmable i/o the series 4 pio addresses the demand for the flexi- bility to select i/os that meet system interface require- ments. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the flexibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multi- plies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication stan- dards permitting the device to hook up directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed, single- ended, and differential-pair signaling (as shown in table 1). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v referenced output levels. routing the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as buses with related control signals. both local and glo- bal signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half-chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great flexibility in moving signals to and from the logic core. this flexibil- ity translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins.
10 10 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc system-level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block rams, univer- sal programmable phase-locked loops, and the addi- tion of highly tuned networking specific phase-locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to vary- ing conditions in today ? s high-speed networking sys- tems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16-, and 32-bit interfaces with optional parity to the motorola ? powerpc 860 bus, it can be used for configuration and readback, as well as for fpga con- trol and monitoring of fpga status. all mpi transac- tions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-defined logic following configuration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4-bytes or less), 4- beat (4 x 4-bytes), 8-beat (8 x 2-bytes), or 16-beat (16 x 1-bytes). system bus an on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the mpi, con- figuration logic, fpga control, and status registers, embedded block rams, as well as user logic. utilizing the amba specification rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user-logic and embedded back- plane transceiver portion of the 8850. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset functions, and pll programming. status registers monitor init, done, and system bus errors. an inter- rupt controller is integrated to provide up to eight possi- ble interrupt resources. bus clock generation can be sourced from the microprocessor interface clock, con- figuration clock (for slave configuration modes), inter- nal oscillator, user clock from routing, or from the port clock (for jtag configuration modes). phase-locked loops up to eight plls are provided on each series 4 device, with four plls generally provided for fpscs. program- mable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clocks from 20 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programma- ble pll provides two outputs that have different multi- plication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two out- puts that can have programmable (12.5% steps) phase differences. additional highly tuned and characterized, dedicated phase-locked loops (dplls) are included to ease sys- tem designs. these dplls meet itu-t g.811 primary- clocking specifications and enable system designers to very tightly target specified clock conditioning not tradi- tionally available in the universal pplls. initial dplls are targeted to low-speed networking ds1 and e1, and also high-speed sonet/sdh networking sts-3 and stm-1 systems. these dplls are typically not included on fpsc devices and are not found on the ort8850 family. embedded block ram new 512 x 18 quad-port ram blocks are embedded in the fpga core to significantly increase the amount of memory and complement the distributed pfu memo- ries. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow signifi- cant flexibility for fifo, constant multiply, and two-vari- able multiply functions. the user can configure fifo blocks with flexible depths of 512k, 256k, and 1k including asynchronous and synchronous modes and programmable status and error flags. multiplier capabil- ities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multi- ply of two 8-bit numbers (16-bit output). on-the-fly coefficient modifications are available through the sec- ond read/write port. two 16 x 8-bit cams per embed- ded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be pre- loaded at device configuration time.
agere systems inc. 11 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc system-level features (continued) configuration the fpgas functionality is determined by internal con- figuration ram. the fpgas internal initialization/con- figuration circuitry loads the configuration data at powerup or under system control. the configuration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for configuring fpgas. the ram is loaded by using one of several configura- tion modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous periph- eral modes, the series 4 also utilizes its microproces- sor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial reconfiguration are also permitted. other configuration options include the initialization of the embedded-block ram memories and fpsc mem- ory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available meeting in- system programming (isp) standards ( ieee 1532 draft). additional information contact your local agere representative for additional information regarding the orca series 4 fpga devices, or visit our website at: http://www.agere.com/orca
12 12 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc ort8850 overview device layout the ort8850 fpsc provides a high-speed backplane transceiver combined with fpga logic. the device is based on 1.5 v or4e2 or or4e6 fpgas. the or4e2 has a 26 x 24 array of programmable logic cells (plcs) and the or4e6 has a 46 x 44 array. for the ort8850, several columns of plcs in these arrays were replaced with the embedded backplane transceiver core. the ort8850 embedded core comprises a long-haul interface macro and three rapidio macros for intra- board chip-to-chip or backplane communication. the long-haul interface includes the high-speed interface (hsi) macrocell, the synchronous transport module (stm) macrocell, and a 8b/10b encoder/decoder. the eight full-duplex channels perform data transfer, scram- bling/descrambling or encoding/decoding, and framing at the rate of 850 mbits/s. each rapidio block has a transmit and receive section that each contain one lvds clock buffer pair, one lvds start-of-cell buffer pair, and eight lvds clock buffer pairs which are dou- ble edge clocked by the corresponding clock. figure 1 shows the ort8850 block diagram. backplane transceiver interface the advantage of the ort8850 fpsc is to bring spe- cific networking functions to an early market presence using programmable logic in a system. the 850 mbits/s backplane transceiver core allows the ort8850 to communicate across a backplane or on a given board at an aggregate speed of 6.8 gbits/s, pro- viding a physical medium for high-speed asynchronous serial data transfer between system devices. this device is intended for, but not limited to, connecting ter- minal equipment in sonet/sdh, atm, and ip sys- tems. the backplane transceiver core is used to support a 6.8 gbits/s interface for backplane connection to a mate tadm042g5 device or other sonet devices such as redundant central crossconnect. the interface is implemented as an eight-channel 850 mbits/s lvds links. the hsi macrocell is used for clock/data recov- ery (cdr) and serialize/deserialize between the 106.25 mhz byte-wide internal data buses and the 850 mbits/s serial lvds links. for a 622 mbits/s sonet stream, the hsi will perform clock and data recovery (cdr) and mux/demux between 77.76 mhz byte-wide internal data buses and 622 mbits/s serial lvds links. each 850 mbits/s serial link uses a pseudo-sonet protocol. sonet a1/a2 framing is used on the link to detect the 8 khz frame location. the link is also scram- bled using the standard sonet scrambler definition to ensure proper transitions on the link for improved cdr performance. selectable transport overhead (toh) bytes are insertable in the transmit direction. all the selectable bytes are inserted from software program- mable registers that are accessed via a microproces- sor interface. elastic buffers (fifos) are used to align each incoming sts-12 link to the 77.76 mhz clock and 8 khz frame. these fifos will absorb delay variations between the four 622 mbits/s links due to timing skews between cards and along backplane traces. for greater varia- tions, a streamlined pointer processor (pointer mover) within the stm macro will align the 8 khz frames regardless of their incoming frame position. the backplane transceiver allows for sonet scram- bling and frame alignment or 8-bit/10-bit (8b/10b) encoding/decoding. sonet has the advantage of reduced overhead (3.3% overhead for sonet vs. 25% overhead for 8b/10b). 8b/10b has the advantage of faster synchronization (a few bytes of transferred data for 8b/10b vs. up to 500 s for four frames of data for sonet). the effective data transfer rate for scrambled sonet is greater than 800 mbits/s while the effective data transfer rate for 8b/10b is greater than 680 mbits/s. frame synchronization and multichannel alignment is provided in 8b/10b mode through the use of special k characters. figure 2 shows the architecture of the ort8850 back- plane transceiver core.
agere systems inc. 13 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc ort8850 overview (continued) 1729(f) figure 1. orca ort8850 block diagram standard fpga i/os orca series 4 fpga logic lvds i/os 311 mhz ddr interface 8-bit/10-bit encoder 8-bit/10-bit decoder pseudo- sonet framer ? pointer mover ? scrambling ? fifo alignment ? selected toh clock/data recovery byte- wide data lvds 850 mbits/s data 850 mbits/s data 8 full- serial duplex channels lvds i/os lvds i/os i/os ( rapidio ) 311 mhz ddr interface ( rapidio ) 311 mhz ddr interface ( rapidio )
14 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc ort8850 overview (continued) figure 2. high-level diagram of ort8850 transceiver io ring soft cntl txd_a[7:0] txsoc_a txclk_a rxd_a[7:0] rxsoc_a rxclk_a transmit rstn_rx_a csysenb_a txd[31:0] txsoc ytristn_a utxtristn_a rstn_utx_a utxd_a[31:0] utxsoc_a pll wcd fpga wutxclk_fpga zrxd_a[31:0] zrxsoc_a zrxsocviol_a zrxalnviol_a zrxclk_a wrxclk_a_fpga pfclk stm macro + cdr 8 8 tx rx 8 8 2 1 4 12x8 8 10 9 1 9x8 (8 channels) 8 data + par 8b/10b k-control inputs line_fp, sys_fp sys_clk prot_sw 8 data + spe + c1j1 + par +en 8 recovered clks toh block 8 data + toh_ck_en + toh_fp 8 data + toh_ck_en toh_clk cdr + stm rapidio a up interface pwruprst from fpga (goes to all blocks) system bus fifo transm it module receive module soft cntl txd_b[7:0] txsoc_b txclk_b rxd_b[7:0] rxsoc_b rxclk_b transmit rstn_rx_b csysenb_b txd[31:0] txsoc ytristn_b utxtristn_b rstn_utx_b utxd_b[31:0] utxsoc_b wcd wutxclk_fpga zrxd_b[31:0] zrxsoc_b zrxsocviol_b zrxalnviol_b zrxclk_b wrxclk_b_fpga pfclk rapidio b fifo transm it module receive module soft cntl txd_c[7:0] txsoc_c txclk_c rxd_c[7:0] rxsoc_c rxclk_c transmit rstn_rx_c csysenb_c txd[31:0] txsoc ytristn_c utxtristn_c rstn_utx_c utxd_c[31:0] utxsoc_c wcd wutxclk_fpga zrxd_c[31:0] zrxsoc_c zrxsocviol_c zrxalnviol_c zrxclk_c wrxclk_c_fpga pfclk rapidio c fifo transm it module receive module soft cntl 8 soft cntl 8
agere systems inc. 15 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc ort8850 overview (continued) hsi interface the high-speed interconnect (hsi) macrocell is used for clock/data recovery and mux/demux between 106.25 mhz byte-wide internal data buses and 850 mbits/s external serial links. the hsi interface receives eight 850 mbits/s serial input data streams from the lvds inputs and provides eight independent 106.25 mhz byte-wide data streams and recovered clock to the stm macro. there is no requirement for bit alignment since sonet type fram- ing will take place inside the ort850 core. for trans- mit, the hsi converts four byte-wide 106.25 mhz data streams to serial streams at 850 mbits/s at the lvds outputs. stm macrocell the stm portion of the embedded core consists of transmitter (tx) and receiver (rx) sections. the receiver receives eight byte-wide data streams at 106.25 mhz and the associated clocks from the hsi. in the rx section, the incoming streams are sonet framed and descrambled before they are written into a fifo, which absorbs phase and delay variations and allows the shift to the system clock. the toh is then extracted and sent out on the eight serial ports. the pointer mover consists of three blocks: pointer inter- preter, elastic store, and pointer generator. the pointer interpreter finds the synchronous transport signal (sts) synchronous payload envelopes (spe) and places it into a small elastic store from which the pointer generator will produce eight byte-wide sts-12 streams of data that are aligned to the system timing pulse. in the tx section, transmitted data for each channel is received through a parallel bus and a serial port from the fpga circuit. toh bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the sts-12 frame via the toh processor. each of the eight parallel input buses is synchronized to a free-running system clock. then the spe and toh data is transferred to the hsi. the stm macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scram- bler of the transmitter and the descrambler of the receiver. also, unused channels can be disabled to reduce power dissipation. 8b/10b encoder/decoder the ort8850 facilitates high-speed serial transfer of data in a variety of applications including gigabit ether- net, fibre channel, serial backplanes, and proprietary links. the device provides 8b/10b coding/decoding for each channel. the 8b/10b transmission code includes serial encoding/decoding rules, special characters, and error detection. information to be transmitted over a fibre shall be encoded eight bits at a time into a 10-bit transmission character and then sent serially. the 10-bit transmis- sion characters support all 256 eight-bit combinations. some of the remaining transmission characters referred to as special characters, are used for functions which are to be distinguishable from the contents of a frame. fpga interface the fpga logic will receive/transmit frame-aligned (optional for 8b/10b mode) streams of 106.25 mhz data (maximum of eight streams in each direction) from/to the backplane transceiver embedded core. all frames transmitted to the fpga will be aligned to the fpga frame pulse which will be provided by the fpga user ? s logic to the stm macro. if the receive pointer mover and alignment fifos are bypassed, then each channel will provide its own receive clock and receive frame pulse signals. otherwise, all frames received from the fpga logic will be aligned to the system frame pulse that will be supplied to the stm macro from the fpga user ? s logic. byte-wide parallel interface three byte-wide parallel interface are provided on the ort8850. each interface provides for transmit and receive of byte-wide data, one control signal, and one clock. receive data is sampled on both edges of the receive clock and is converted to a 32-bit data bus, which is single-edge clocked by a half-speed clock for transfer to the fpga logic. maximum transmit/receive clock rate is 311 mhz and 155 mhz for the internal fpga clock. this allows for a 622 mbits/s link data transfer rate. other functions provided include a check for a minimum number of transferred bytes. the first byte-wide interface ( rapidio a in figure 2) is always available. the other two interfaces ( rapidio b and rapidio c) are available when the 850 mbits/s serial links are not being used.
16 16 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc ort8850 overview (continued) fpsc configuration configuration of the ort8850 occurs in two stages: fpga bit stream configuration and embedded core setup. fpga configuration prior to becoming operational, the fpga goes through a sequence of states, including powerup, initialization, configuration, start-up, and operation. the fpga logic is configured by standard fpga bit stream configura- tion means as discussed in the series 4 fpga data sheet. the options for the embedded core are set via registers that are accessed through the fpga system bus. the system bus can be driven by an external ppc compliant microprocessor via the mpi block or via a user master interface in fpga logic. a simple ip block, that drives the system by using the user interface and uses very little fpga logic, is available in the mpi/sys- tem bus application note (ap01-032ncip). this ip block sets up the embedded core via a state machine and allows the ort8850 to work in an independent system without an external microprocessor interface. embedded core setup all options for the operation of the core are configured according to the device register map, which is included with the ort8850 fpsc simulation kit. during the powerup sequence, the ort8850 device (fpga programmable circuit and the core) is held in reset. all the lvds output buffers and other output buffers are held in 3-state. all flip-flops in the core area are in reset state, with the exception of the boundry- scan shift registers, which can only be reset by bound- ary-scan reset. after powerup reset, the fpga can start configuration. during fpga configuration, the ort8850 core will be held in reset and all the local bus interface signals forced high, but the following active- high signals (prot_switch_a, prot_switch_c, tx_toh_ck_en, sys_fp, line_fp) will be forced low. the core_ready signal sent from the embed- ded core to fpga is held low, indicating that the core is not ready to interact with fpga logic. at the end of the fpga configuration sequence, the core_ready sig- nal will be held low for six sys_clk cycles after done, tri_io and rst_n (core global reset) are high. then it will go active-high, indicating the embed- ded core is ready to function and interact with fpga programmable circuit. during fpga reconfiguration when done and tri_io are low, the core_ready signal sent from the core to fpga will be held low again to indicate the embedded core is not ready to interact with fpga logic. during fpga partial configu- ration, core_ready stays active. the same fpga configuration sequence described previously will repeat again. the initialization of the embedded core consists of two steps: register configuration and synchronization of the alignment fifo. in order to configure the embedded core, the registers need to be unlocked by writing 0x30005 to address 0x30004 and writing 0x80 to address 0x05. control registers 0x30004 and 0x30005 are lock registers. if the output bus of the data, serial toh port, and toh clock and toh frame pulse are controlled by 3-state registers (the use of the registers for 3-state output control is optional; these output 3- state enable signals are brought across the local bus interface and available to the fpga side), the next step is to activate the 3-state output bus and signals by tak- ing them to functional state from high-impedance state. this can be done by writing 0x01 to correspond bits of the channel registers 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30090, 0x300b0, and 0x300c8. in addition, the synchronization of selected streams is recommended for some networking systems applica- tions. this requires a resync of the alignment fifo after the enabled channels have a valid frame pulse or 8b/10b control character. see the sections about stm link alignment setup or 8b/10b link alignment setup for more details.
agere systems inc. 17 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc generic backplane transceiver application synchronous transfer mode (stm) the combination of ort8850 and soft ip cores pro- vides a generic data moving solution for non-sonet applications. there is no requirement for sonet knowledge to the users. all that is needed is to supply the pseudo-sonet framer with data, clock, and a 8 khz frame pulse. the provision registers may also need to be set up, and this can be done through either the fpga mpi, or in a state machine in the fpga sec- tion (vhdl code available from agere). the 8 khz frame pulse must be supplied to the sys_fp signal. for generic applications, the frame pulse can be created in fpga logic from the 77.76 mhz sys_clk using a simple resettable counter (the frame pulse should only be high for one cycle of the sys_clk). a vhdl core that automati- cally provides the 8 khz frame pulse is available from agere. byte-wide data is then sent to each of the trans- mit channels as follows: the first 36 bytes transferred will be invalid data (replaced by overhead), where the first byte is sent on the rising edge of sys_clk when sys_fp is high. the next 1044 byte positions can be filled with valid data. this will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 khz frame pulse will be found. thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data. the ort8850 also supports a transparent mode where only the first 24 bytes are invalid data (a1/a2 frame bytes) followed by 9,684 bytes of valid user data. on the receive side, an 8 khz pulse must again be sup- plied to line_fp. in this case, however, only the signal dout_spe (where the eight channels are labeled aa, ab, ac, ad, ba, bb, bc, and bd) must be monitored for each channel, where a high value on this signal means valid data. again, 87 out 90 bytes received (96.7%) will be valid data. transparent mode is also supported for receive data. 8b/10b mode the ort8850 facilitates high-speed serial transfer of data in a variety of applications including gigabit ethernet, fibre channel, serial backplanes, and proprietary links. in place of the stm interface, the ort8850 also provides 8b/10b coding/decoding for each channel. the 8b/10b transmission code includes serial encoding/decoding rules, special characters, and error detection. in 8b/10b mode, lsb is received first and transmitted first. the 10-bit encoded transmission characters labeled as a, b, c, d, e, i, f, g, h, and j are transmitted with bit a first and bit j last, where bit a is the lsb and bit j is the msb. transmitter description the data input to the transmitter of each channel is an 8-bit word and a k-control input. the k input is used to identify data or a special character. for each channel, the input data byte is clocked into a fifo. when k-con- trol is 1, the data on the parallel input is mapped into its corresponding control character. the transmit fifos must be initialized upon the deassertion of the rst_n signal. receiver description clock recovery is performed by the hsi on the input data stream for each channel of the ort8850. the recovered data is then aligned to the 10-bit word boundary. word alignment is accomplished by detect- ing and aligning to the 8b/10b comma sequence. the hsi will detect and align to either polarity of the comma sequence. the 10-bit word aligned data is then decoded and the 8-bit output is passed to the align- ment fifos. each receive channel provides a fifo in order to adjust for the skew between the channels and ensure that the first valid data following the comma character is transmitted simultaneously from all the channels that are programmed to be aligned. in the reset state, each channel is actively searching for the occurence of a comma character. once the channel is powered up, the comma detect pulse will be found on the doutxx-fp per channel in the fpga. receive channel sync block in order to account for skews between the channels, it is necessary to align multiple channels on the comma character boundary. the sync algorithm assumes that either all eight channels, two groups of four channels, or four groups of two channels will be aligned. the ort8850 powers up in the reset state in which no channel alignment is done.
18 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc generic backplane transceiver application (continued) 1757(f) figure 3. 8850 with 8b/10b coding/decoding clock recovery rx lvds tx lvds data clock 10 lckrx deserializer and byte align receiver channel (1 of 8) 10b/8b decoder alignment fifo parallel data out sys_clk comma _det doutxx_fp error flag parallel datain fifo 8 10 transmit channel (1 of 8) 8b/10b encoder serializer doutxx dinxx backplane transceiver core detailed description hsi macro the 850 high-speed interface (hsi) provides a physical medium for high-speed asynchronous serial data trans- fer between asic devices. the devices can be mounted on the same pc board or mounted on differ- ent boards and connected through the shelf back- plane. the 850 cdr macro is an eight-channel clock- phase select (cps) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. the macrocell can be used as a eight-channel or 16-channel configuration. the ort8850 uses an eight- channel hsi macro cell. the hsi macro consists of three functionally independent blocks: receiver, trans- mitter, and pll synthesizer as shown in figure 4. the pll synthesizer block generates the necessary 850 mhz clock for operation from a 212 mhz, 106 mhz, or 85 mhz reference. the pll synthesizer block is a common asset shared by all eight receive and transmit channels. the pll reference clock must match the interface frequency. the hsi_rx block receives a differential 850 mbits/s (or subrates 424 mbits/s, 212 mbits/s) serial data with- out clock at its lvds receiver input. based on data transitions, the receiver selects an appropriate 850 mhz clock phase for each channel to retime the data. the retimed data and clock are then passed to the demux (deserializer) module. demux module per- forms serial-to-parallel conversion and provides three possible parallel rates, 212 mbits/s, 106 mbits/s, or 85 mbits/s, where the 106 mbits/s data is used in sonet mode and the 85 mbits/s data is used in 8b/10b mode (212 mbits/s is unused). the hsi_tx block receives 106 mbits/s (sonet mode), or 85 mbits/s (8b/10b mode) parallel data at its input. mux (serializer) module performs a parallel-to- serial conversion using an 850 mhz clock provided by the pll/synthesizer block. the resulting 850 mbits/s serial data stream is then transmitted through the lvds driver. the loopback feature built into the hsi macro provides looping of the transmitter data output into the receiver input when desired. all rate examples described here are the maximum rates possible. the actual hsi internal clock rate is determined by the provided reference clock rate. for example, if a 78 mhz reference clock is provided, the hsi macro will operate at 622 mbits/s.
agere systems inc. 19 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) 5-8592(f).b figure 4. hsi functional block diagram rx cdr serial to parrallel demux select 848 mhz clock/data alignment synthesizer pll loopbkch[(n ? 1):0] ld[(n ? 1):0]rx[9:0] tstclk creg bypass creg loopbken din[(n ? 1):0] 848 mbits/s sysclk 106 mhz dout[(n ? 1):0] (test) lckrx[(n ? 1):0] tstclk bypass (test) rxpwrdn[(n ? 1):0] lckpll 106 mbits/s ld[(n ? 1):0] tx[9:0] 1 2 n tx 1 2 n retime or 85 mhz or 424 mbits/s or 212 mbits/s data or 85 mbits/s parrallel to serial mux word align ten bit rc[1:0]ck[(n ? 1):0] encomma[(n ? 1):0] commadet[(n ? 1):0] mode control en10bit (850 mhz) resettx resetrx 848 mbits/s or 424 mbits/s or 212 mbits/s data 106 mbits/s or 85 mbits/s 106 mhz or 85 mhz 106 mbits/s or 85 mbits/s to asic block
20 20 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) stm transmitter (fpga backplane) the synchronous transport module (stm) portion of the embedded core consists of two slices: stm a and b. each stm slice has four sts-12 transmit channels, which can be treated as a single sts-48 channel. in general, the transmitter circuit receives four byte-wide 77.76 mhz data from the fpga, which nominally rep- resents four sts-12 streams (a, b, c, and d). this data is synchronized to the system (reference) clock, and an 8 khz system frame pulse from the fpga logic. transport overhead bytes are then optionally inserted into these streams, and the streams are forwarded to the hsi. all byte timing pulses required to isolate indi- vidual overhead bytes (e.g., a1, a2, b1, d1 ? d3, etc.) are generated internally based on the system frame pulse (sys_fp) received from the fpga logic. all streams operate byte-wide at 77.76 mhz in all modes. the toh processor operates from 25 mhz to 77.76 mhz and supports the following toh signals: a1 and a2 insertion and optional corruption; h1, h2, and h3 pass transparently; bip-8 parity calculation (after scrambling) and b1 byte insertion and optional corrup- tion (before scrambling); optional k1 and k2 insert; optional s1/m0 insert; optional e1/f1/e2 insert; optional section data communication channel (dcc, d1 ? d3) and line data communication channel (dcc, d4 ? d12) insertion (for intercard communications channel); scrambling of outgoing data stream with optional scrambler disabling; and optional stream dis- abling. all streams operate byte-wide at 77.76 mhz (622 mbits/s) or 106.25 mhz (850 mbits/s) in all modes. when the ort8850 is used in nonnetworking applica- tions as a generic high-speed backplane data mover, the toh serial ports are unused or can be used for slow-speed, off-channel communication between devices. an optional transparent mode is available where only the twelve a1 and twelve a2 bytes are used for frame alignment and synchronization. data received on the parallel bus is optionally scram- bled and transferred to lvds outputs. byte ordering information the stm macro slice (i.e., a, b) supports quad sts- 12, quad sts-3, and quad sts-1 modes of operation on the input/output ports. sts-48 is also supported, but it must be received in the quad sts-12 format. when operating in quad sts-12 mode, each of the indepen- dent byte streams carries an entire sts-12 within it. figure 5 reveals the byte ordering of the individual sts-12 streams and for sts-48 operation. note that the recovered data will always continue to be in the same order as transmitted. 5-8574 (f) figure 5. byte ordering of input/output interface in sts-12 mode 12 24 36 48 9 21 33 45 6 18 30 42 3 15 27 39 11 23 35 47 8 20 32 44 5 17 29 41 2 14 26 38 10 22 34 46 7 19 31 43 4 16 28 40 1 13 25 37 1, 12 2, 12 3, 12 4, 12 1, 9 2, 9 3, 9 4, 9 1, 6 2, 6 3, 6 4, 6 1, 3 2, 3 3, 3 4, 3 1, 11 2, 11 3, 11 4, 11 1, 8 2, 8 3, 8 4, 8 1, 5 2, 5 3, 5 4, 5 1, 2 2, 2 3, 2 4, 2 1, 10 2, 10 3, 10 4, 10 1, 7 2, 7 3, 7 4, 7 1, 4 2, 4 3, 4 4, 4 1, 1 2, 1 3, 1 4, 1 sts-12 a sts-12 b sts-12 c sts-12 d sts-12 a sts-12 b sts-12 c sts-12 d sts-48 in quad sts-12 format quad sts-12
agere systems inc. 21 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) transport overhead for in-band communication the toh byte can be used for in-band configuration, service, and management since it is carried along the same channel as data. in ort8850, in-band signaling can be efficiently utilized, since the total cost of over- head is only 3.3%. transport overhead insertion (serial link) the toh serial links are used to insert toh bytes into the transmit data. the transmit toh data and toh_clk_en get retimed by toh_clk in order to meet setup and hold specifications of the device. the retimed toh data is shifted into a 288-bit (36-byte by 8-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. insertion from these serial links or pass-through of toh from the byte-wide data is under software control. transport overhead byte ordering (fpga to backplane) in the transparent mode, spe and toh data received on parallel input bus is transferred, unaltered, to the serial lvds output. however, b1 byte of sts#1 is always replaced with a new calculated value (the 11 bytes following b1 are replaced with all zeros). also, a1 and a2 bytes of all sts-1s are always regenerated. toh serial port in not used in the transparent mode of operation. in the toh insert mode, spe bytes are transferred, unaltered, from the input parallel bus to the serial lvds output. on the other hand, toh bytes are received from the serial input port and are inserted in the sts- 12 frame before being sent to the lvds output. although all toh bytes from the 12 sts-1s are trans- ferred into the device from each serial port, not all of them get inserted in the frame. there are three hard- coded exceptions to the toh byte insertion: framing bytes (a1/a2 of all sts-1s) are not inserted from the serial input bus. instead, they can always be regenerated. parity byte (b1 of sts#1) is not inserted from the serial input bus. instead, it is always recalculated (the 11 bytes following b1 are replaced with all zeros). pointer bytes (h1/h2/h3 of all sts-1s) are not inserted from the serial input bus. instead, they always flow transparently from parallel input to lvds output. in addition to the above hardcoded exceptions, the source of some toh bytes can be further controlled by software. when configured to be in pass-through mode, the specific bytes must flow transparently from the parallel input. note that blocks of 12 sts-1 bytes forming an sts-12 are controlled as a whole. there are 15 software controls per channel, as listed below: source of k1 and k2 bytes of the 12 sts-1s (24 bytes) is specified by a control bit (per channel control). source of s1 and m0 bytes of the 12 sts-1s (24 bytes) is specified by a control bit (per channel control). source of e1, f1, e2 bytes of the sts-1s (36 bytes) is specified by a control it (per channel control). source of d1 bytes of the sts-1s (12 bytes) is spec- ified by a control bit (per channel control). source of d2 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d3 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d4 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d5 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d6 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d7 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d8 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d9 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d10 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d11 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). source of d12 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). toh reconstruction is dependent on the transmitter mode of operation. in the transparent mode, toh bytes on lvds output are as shown in table 2. a new capability in the ort8850 allows the user to choose not to insert the b1 byte and the following 11 bytes of zeros. this option is also available for the a1 and a2 bytes.
22 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) table 2. transmitter toh on lvds output (transparent mode) in the toh insert mode of operation, toh bytes on lvds output are shown in table 3. this also shows the order in which data is transferred to the serial toh interface, starting with the most significant bit of the first a1 byte. the first bit of the first byte is replaced by an even parity check bit over all toh bytes from the previous toh frame. table 3. transmitter toh on lvds output (toh insert mode) a1/a2 frame insert and testing the a1 and a2 bytes provide a special framing pattern that indicates where a sts-1 begins in a bit stream. all 12 a1 bytes of each sts-12 are set to 0xf6, and all 12 a2 bytes of the sts-12 are set to 0x28 when not overrid- den with an user-specified value for testing. the latency from the transmission of the first bit of the a1 byte at the device output pins from the transmit frame pulse (sys_fp) at the fpga to embedded core input is between five to seven cycles of fpga_sysclk. a1/a2 testing (corruption) is controlled per stream by the a1/a2 error insert register. when a1/a2 corruption detec- tion is set for a particular stream, the a1/a2 values in the corrupted a1/a2 value registers are sent for the number of frames defined in the corrupted a1/a2 frame count register. when the corrupted a1/a2 frame count register is set to zero, a1/a2 corruption will continue until the a1/a2 error insert register is cleared. this also allows alternate values to be set for a1 and a2 during normal operation. for the ort8850, it is optionally possible to not insert a1 and a2. on a per-device basis, the a1 and a2 byte values are set, as well as the number of frames of corruption. then, to insert the specified a1/a2 values, each channel has an enable register. when the enable register is set, the a1/a2 values are corrupted for the number specified in the number of frames to corrupt. to insert errors again, the per- channel fault insert register must be cleared, and set again. only the last a1 and the first a2 are corrupted. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 regenerated bytes. transparent bytes from parallel input port. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 regenerated bytes. inserted or transparent bytes. blocks of 12 sts-1 bytes are controlled as a whole. there are 15 controls/channel: k1/k2, s1/m0, e1/f1/e2, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12. transparent bytes (from parallel input port). inserted bytes from toh serial input port.
agere systems inc. 23 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) b1 calculation and insertion in a bit interleaved parity -8 (bip-8) error check set for even parity over all the bits of an sts-1 frame b1 is defined for the first sts-1 in an sts-n only, the b1 cal- culation block computes a bip-8 code, using even par- ity over all bits of the previous sts-12 frame after scrambling and is inserted in the b1 byte of the current sts-12 frame before scrambling. per-bit b1 corruption is controlled by the force bip-8 corruption register (reg- ister address 0f). for any bit set in this register, the corresponding bit in the calculated bip-8 is inverted before insertion into the b1 byte position. each stream has an independent fault insert register that enables the inversion of the b1 bytes. b1 bytes in all other sts- 1s in the stream are filled with zeros. for the ort8850, it is optionally possible to not insert b1 and the subse- quent 11 bytes of zeros. stream disable when disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the hsi. the hsi macro is pow- ered down on a per-stream basis, as are its lvds out- puts. scrambler the data stream is scrambled using a frame-synchro- nous scrambler with a sequence length of 127. the scrambling function can be disabled by software. the generating polynomial for the scrambler is 1 + x 6 + x 7 . this polynomial conforms to the standard sonet sts-12 data format. the scrambler is reset to 1111111 on the first byte of the spe (byte following the z0 byte in the twelfth sts-1). that byte and all subsequent bytes to be scrambled are exclusive-ored, with the output from the byte-wise scrambler. the scrambler runs continuously from that byte on throughout the remainder of the frame. a1, a2, j0, and z0 bytes are not scrambled. system frame pulse and line frame pulse system frame pulse (for transmitter) and line frame pulse (for receiver) are generated in fpga logic. a1/a2 framing is used on the link for locating the 8 khz frame location. all frames sent to the fpga are aligned to the fpga frame pulse line_fp which is provided by the fpga to the stm macro. all frames sent from the fpga to the stm will be aligned to the frame pulse sys_fp that is supplied to the stm macro. in either direction, the system frame pulse and line frame pulse are active for one system clock cycle, indicating the location of a1 byte of sts#1. they are common to all eight channels except when the pointer mover and alignment fifos are bypassed. in that case, a line frame pulse for each receive channel is generated by the stm macro and passed to the fpga interface. repeater this block is essentially the inverse of the sampler block. it receives byte-wide sts-12 rate data from the toh insert block. in order to support the quad sts-1 and sts-3 modes of operation, the hsi (622 mbits/s) can be connected to a slower speed device (e.g., 155 mbits/s or 52 mbits/s). the purpose of this block is to rearrange the data being fed to the hsi so that each bit is transmitted four or twelve times, thus simulating 155 mbits/s or 51.84 mbits/s serial data. for example, in sts-3 mode, the incoming sts-12 stream is com- posed of four identical sts-3s so only every fourth byte is used. the bit expansion process takes a single byte and stretches it to take up 4 bytes each consisting of 4 copies of the 8 bits from the original byte. in sts-1 mode, every twelfth byte is used and four groups of 3 bytes of the form aaaaaaaa, aaaabbbb, and bbbbbbbb are forwarded to the hsi. an alternate method for supplying sts-1 mode is to set the hsi to run at 207.36 mhz and use the four times repeater function. stm receiver (backplane fpga) each of the two stm slices of the ort8850 has four receiving channels that can be treated as one sts-48 stream, or treated as independent channels. incoming data is received through lvds serial ports at the data rate of 622 mbits/s. the receiver can handle the data streams with frame offsets of up to 12 bytes which would be due to timing skews between cards and along backplane traces or other transmission medium. in order for this multichannel alignment capability to oper- ate properly, it should be noted that while the skew between channels can be very large, they must oper- ate at the exact same frequency (0 ppm frequency deviation), thus requiring that their transmitters be driven by the same clock source. the received data streams are processed in the hsi and the stm, and then passed through the cic boundary to the fpga logic.
24 24 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) framer block the framer block takes byte-wide data from the hsi, and outputs a byte-aligned, byte-wide data stream and 8 khz sync pulse. the framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (oof) state. the framer detects the a1/ a2 framing pattern and generates the 8 khz frame pulse. when the framer detects oof, it will generate an interrupt. also, the framer detects an errored frame and increments an a1/a2 frame error counter. the counter can be monitored by a processor to compile performance status on the quality of the backplane. because the ort8850 is intended for use between it and another ort8850 or other devices via a back- plane, there is only one errored frame state. thus, after two transitions are missed, the state machine goes into the oof state and there is no severely errored frame (sef) or loss-of-frame (lof) indication. b1 calculate each rx block receives byte-wide scrambled 77.76 mhz data and a frame sync from the framer. since each hsi is independently clocked, the rx block operates on individual streams. timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. the rx block pro- duces byte-wide (optionally) descrambled data and an output frame sync for the alignment fifo block. the frame sync signals are also sent to the fpga logic for use when the alignment fifo block is bypassed. the b1 calculation block computes a bip-8 (bit inter- leaved parity 8 bits) code, using even parity over all bits of the previous sts-12 frame before descrambling; this value is checked against the b1 byte of the current frame after descrambling. a per-stream b1 error counter is incremented for each bit that is in error. the error counter may be read via the cpu interface. descrambling. the streams are descrambled using a frame synchronous descrambler with a sequence length of 127 with a generating polynomial of 1 + x 6 + x 7 . the a1/a2 framing bytes, the section trace byte (j0) and the growth bytes (z0) are not descrambled. the descrambling function can be disabled by soft- ware. sampler. this block operates on the byte-wide data directly from the hsi macro. the hsi external interface always runs at 622 mbits/s (sts-12), or 850 mbits/s, but it can be connected directly to a 155 mbits/s sts-3 stream or a 51.84 mbits/s sts-1 stream. if connected to either a 155 mbits/s or 51.84 mbits/s stream, each incoming data is received either 4 or 12 times respec- tively. this block is used to return the byte stream to the expected sts-12 format. the mode of operation is controlled by a register and can either be sts-12 (pass-through), sts-3 (every fourth bit), or sts-1 (every twelfth bit). the output from this block is not bit- aligned (i.e., an 8-bit sample does not necessarily con- tain an entire sonet byte), but it is in standard sonet sts-12 format (i.e., four sts-3s or 12 sts- 1s) and is suitable for framing. ais-l insertion. alarm indication signal (ais) is a con- tinuous stream of unframed 1s sent to alert down- stream equipment that the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. if enabled in the ais_l force reg- ister, ais-l is inserted into the received frame by writ- ing all ones for all bytes of the descrambled stream. ais-l insertion on out-of-frame. if enabled via a register, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condi- tion exists. internal parity generation even parity is generated on all data bytes and is routed in parallel with the data to be checked before the pro- tection switch mux at the parallel output.
agere systems inc. 25 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) transport overhead extraction transport overhead is extracted from the receive data stream by the toh extract block. the incoming data gets loaded into a 36-byte shift register on the system clock domain. this, in turn, is clocked onto the toh clock domain at the start of the spe time, where it can be clocked out. during the spe time, the receiver toh frame pulse is generated, rx_toh_fp, which indicates the start of the row of 36 toh bytes. this pulse, along with the receive toh clock enable, rx_toh_ck_en, as well as the toh data, are all launched on the rising edge of the toh clock toh_clk. toh byte ordering the toh processor is responsible for dropping all toh bytes of each channel through one of four corresponding serial ports. the four toh serial ports are synchronized to the toh clock (the same clock that is being used by the serial ports on the transmitter side). this free-running toh clock is provided to the core by external circuitry and operates at a minimum frequency of 25 mhz and a maximum frequency of 77.76 mhz. data is transferred over serial links in a bursty fashion as controlled by the rx toh clock enable signal, which is generated by the asic and common to the four channels. all toh bytes of sts-12 streams are transferred over the appropriate serial link in the same order in which they appear in a standard sts-12 frame. data transfer should be preformed on a row- by-row basis such that internal data buffering needs is kept to a minimum. data transfers on the serial links will be synchronized relative to the rx toh frame signal. receiver toh reconstruction receiver toh reconstruction on output parallel bus is as shown in the following table (if the pointer mover is not bypassed). table 4. receiver toh (output parallel bus) on the toh serial port, all toh bytes are dropped as received on the lvds input (msb first). the only exception is the most significant bit of byte a1 of sts#1, which is replaced with an even parity bit. this parity bit is calculated over the previous toh frame. also, on ais-l (either resulting from lof or forced through software), all toh bits are forced to all ones with proper parity (parity automatically ends up being set to 1 on ais-l). special toh byte functions k1 and k2 handling. the k1 and k2 bytes are used in automatic protection switch (aps) applications. k1 and k2 bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the other toh bytes. a1 and a2 handling. as discussed previously, the a1 and a2 bytes are used for a framing header. a1 and a2 bytes are always regenerated and set to hexadecimal f6 and 28, respectively. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 000000000000 k100000000000 k200000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 regenerated bytes. regenerated bytes (under pointer generator control, ss bits must be transparent, ais-p must be supported). bytes taken from elastic store buffer, on negative stuff opportunity-else, forced to all zeros. transparent or all zeros (k1/k2 are either taken from k1/k2 buffer or forced to all zeros-soft, control). in transparent mode, ais-l must be supported. all zero bytes.
26 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) spe and c1j1 outputs . these two signals for each channel are passed to the fpga logic to allow a pointer pro- cessor or other function to extract payload without interpreting the pointers. for the ort8850, each frame has 12 sts-1s. in the spe region, there are 12 j1 pulses for each sts-1s. there is one c1(j0, new sonet specifica- tions use j0 instead of c1 as section trace to identify each sts-1 in an sts-n) pulse in the toh area for one frame. thus, there is a total of 12 j1 pulses and one c1(j0) pulse per frame. c1(j0) pulse is coincident with the j0 of sts1 #1. in each frame, the spe flag is active when the data stream is in spe area. spe behavior is dependent on pointer movement and concatenation. note that in the toh area, h3 can also carry valid data. when valid spe data is carried in this h3 slot, spe is high in this particular toh time slot. in the spe region, if there is no valid data during any spe column, the spe signal will be set to low. spe allows a pointer processor to extract payload with- out interpreting the pointers. the spe and c1j1 functionality are described in table 5. for generic data operation, valid data is available when spe is 1 and the c1j1 signal is ignored. table 5 . spe and c1j1 functionality note:the following rules are observed for generating spe and c1j1 signals: on occurrence of ais-p on any of the sts-1, there is no corre- sponding j1 pulse. in case of concatenated payloads (up to sts48c), only the head sts-1 of the group has an associated j1 pulse . c1j1 signal tracks any pointer movements. during a negative justification event, spe is set high during the h3 byte to indicate that pay- load data is available. during a positive justification event, spe is set low during the positive stuff opportunity byte to ind icate that payload data is not available. 5-9330(f) note: c1j1 signal behavior shown in this figure is just for illustration purposes: c1 pulse position must always be as shown; however , position of j1 pulses vary based on path overhead location of each sts-1 within the sts-12 stream. c1j1 signal must always be active during c1(j0) time slot of sts#1. c1j1 signal must also be active during the twelve j1 time slots. however, c1j1 must not be active for any sts-1 for which ais-p is generated. also, on concatenated payloads, only the head of the group must have a j1 pulse. figure 6. spe and c1j1 functionality spe c1j1 description 0 0 toh information excluding c1(j0) of sts1 #1. 0 1 position of c1(j0) of sts1 #1 (one per frame). typically used to provide a unique link identification (256 possible unique links) to help ensure cards are connected into the backplane correctly or cables are connected correctly. 1 0 spe information excluding the 12 j1 bytes. 1 1 position of the 12 j1 bytes. sts-12 toh row # 1 spe row # 1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 j0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 sts-12 spe c1j1 c1 pulse j1 pulse of 3rd sts-1 first spe bytes of the 12 sts-1s 123456789101112
agere systems inc. 27 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) 5-9331 note: spe signal behavior shown in this figure is just for illustration purposes: spe behavior is dependent on pointer movements and concatenation. spe signal must be high during negative stuff opportunity byte time slots (h3) for which valid data is carried (negative stuffi ng). spe signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing). figure 7. spe stuff bytes stm fifo alignment (backplane fpga) the alignment fifo allows the transfer of all data to the system clock. the fifo sync block (figure 8) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. this optional align- ment ensures that matching sts-12 streams will arrive at the fpga end in perfect data sync. the frame alignment is configurable to allow for the possibility of fully independent (i.e., total frame misalignment) sts-12s. sts-12 toh row # 4 spe row # 4 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 sts-12 spe positive stuff opportunity bytes 123456789101112 negative stuff opportunity bytes spe signal shows negative stuffing for 2nd sts-1, and positive stuffing for 6th sts-1
28 28 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) 5-8577 (f) figure 8. interconnect of streams for fifo alignment the incoming data from the hsi (also referred to as cdrm850) can be separated into four sts-12 chan- nels (a, b, c, and d) per slice. thus, there are sts-12 channels aa to ad from slice a of the stm and sts- 12 channels ba to bd of slice b. these streams can be frame-aligned in the following patterns: in sts-48 mode, all four sts-12s of each stm slice are aligned with each other (i.e., aa, ab, ac, ad). optionally, in sts-48 mode, all eight sts-12s (stms a and b) can be aligned (to allow hitless switching at the sts-48 level). multiple devices can be aligned to enable sts- 192 or higher modes. streams can also be aligned on a twin sts-12 basis. there is also a provision to allow certain streams to be disabled (i.e., not producing inter- rupts or affecting synchronization). these streams can be enabled at a later time without disrupting other streams. if the selected stream needs to be a part of a bigger group (i.e., stm a), then either the entire group must be resynched or the affected stream must have been in the correct mode (i.e., align all stm a) when the initial synchronization was performed. as long as all four streams in stm a are in the correct mode when synchronization takes place, then those streams may be enabled or disabled without affecting synchroniza- tion. these streams can be frame-aligned in the patterns shown in figure 10, figure 9, and figure 11. 0674 figure 9. example of inter-stm alignment 0673(f) figure 10. example of intra-stm alignment 0675 figure 11. example of twin sts-12 stream alignment sts-12 stream aa sts-12 stream ab sts-12 stream ac sts-12 stream ad sts-12 stream ba sts-12 stream bb sts-12 stream bc fifo sync sts-12 stream bd stm slice a stm slice b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d all 8 alignment of stm a and stm b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d t 0 stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d all 4 alignment of stm a and stm b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d t 0 t 1 stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d twins alignment of streams a and c t 0 stm a stream a stm b stream a stm b stream b stm b stream c stm b stream d t 1 stm a stream b stm a stream d stm a stream c
agere systems inc. 29 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) the fifo block consists of a 24-bit by 10-bit fifo per link. this fifo is used to align up to 154.3 ns of inter- link skew and to transfer to the system clock. the fifo sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the first fifo location. on top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). sync and error signals are sent to read control block for alignment. the read control block is synched only once on start-up; any further synchronization is software controlled. the action of resynching a read control block will always cause loss of data. a register allows the read control block to be resynched. stm link alignment the general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the fifo) from the arriving frame pulse and then signal the read control block to begin reading. for perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. the algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. for example (figure 12), if all pulses arrive together, then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the first four pulses and then two per clock afterward, which gives a total of 14 clocks between first frame pulse and the first read. this puts the center of arriving frame pulses at the halfway point in the buffer. this is the extent of the algorithm, and it has no facility for actively correcting problems once they occur. the write control block receives byte-wide data at 77.76 mhz and a frame pulse two clocks before the first a1 byte of the sts-12 frame. it generates the write address for the fifo block. the first a1 in every sts- 12 stream is written in the same location (address 0) in the fifo. also, a frame bit is passed through the fifo along with the first byte before the first a1 of the sts- 12. the read control block synchronizes the reading of the fifo for streams that are to be aligned. reading begins when the fifo sync signals that all of the appli- cable a1s and the appropriate margin have been writ- ten to the fifo. all of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). the alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between sts-12 streams. if this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (align- ment overflow). each sts-12 stream can be realigned by software if it gets too far out of line (this would cause a loss of data). for background applications that have less than 154.3 ns of interlink skew, misalignment will not occur. stm link alignment setup in order to ensure proper operation of the stm link alignment capability, the following setup procedures should be followed after the enabled channels have a valid frame pulse: 1. put all of the streams to be aligned, including dis- abled streams, into their required alignment mode. 2. force ais-l in all streams to be synchronized (refer to register map, write 0x01 to db6 or register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300b0, and 0x300c8). 3. wait four frames. write a 0x01 to the fifo align- ment resync register bits as required in register 0x30017 or 0x30018. wait four frames. 4. release the ais-l in all streams (write 0x00 to db6 or register 0x30020, 0x30038, 0x30050, 0x30068, 0x30080, 0x30098, 0x300b0, and 0x300c8). this procedure allows normal data flow through the embedded core. 5-8584 (f) figure 12. examples of link alignment 24-byte fifo 24-byte fifo all fps 12 clocks sync. pulse arrive together (writing begins) (reading begins) sync pulse (reading begins) last fp arrives 4 clocks first fp arrives (w riting begins) 10 clocks perfectly aligned frames 4-byte spread in arriving frames
30 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) 8b/10b transmitter (fpga backplane) for each channel, an 8b/10b encoder can be enabled in place of the stm transmitter. this block receives 8-bit data from the fpga interface, encodes it into a 10-bit code, and then sends this 10-bit code to the hsi block for serialization and transmission from the ort8850. this 8-bit to 10-bit encoding provides for guaranteed transmis- sion of a large number of transmissions to allow for easy recovery by a cdr on the other end of the backplane or transmission medium, and also allows for the insertion of control characters. these control characters have many uses, including their use in the ort8850 to align 10-bit word boundries and perform multi-channel alignments, as will be discussed in the 8b/10b receiver section. the data input to the transmitter of each channel from the fpga logic is an 8-bit word and k-control input. the k- control input is used to designate data or a special character, where a logic 1 indicates that the data should be mapped to a control character. the following table shows this mapping that is supported. two different codings are possible for each data value and are shown as encoded word (+) and encoded word ( ? ). the transmitter selects between the positive or negative encoded word based on the calculated disparity of the present data. table 6. valid special characters it should also be noted that the data is serialized in the reverse order from the stm block, where dinxy[0] is trans- mitted first (the 8b/10b receive block also deserializes in the reverse order of the stm receive block). 8b/10b receiver (backplane fpga) instead of using the stm receiver block in the ort8850, a separate decoder block is available to allow for receiv- ing data that has been encoded using a standard 8b/10b encoder. this encoding/decoding scheme also allows for the transmission of special characters and allows for error detection. clock recover for the 8b/10b decoder is performed by the hsi block for each of the eight receive channels in the ort8850. this recovered data is then aligned to a 10-bit word boundry by detecting and aligning to the comma- codeword. word alignment is done to either polarity of this codeword. the 10-bit code word is passed to the decoder, which provides an 8-bit byte of data and a commadet signal to the multi-channel alignment block. in 8b/10b mode, the receiver can handle 12 bytes of skew between channels which would be due to timing skews between cards and along backplane trace or other transmission medium. in order for this multi-channel alignment capability to operate properly, it should be noted that while the skew between channels can be very large, they must operate at the exact same frequency (0 ppm frequency deviation), thus requiring their transmitters to be driven by the same clock source. this alignment fifo can be bypassed. the commadet signal is also provided to the fpga logic per channel on the signal doutxy_fp, where x designates either four-channel macro a or b, while y designates the channel (a, b, c, d) in each macro. k character hgf edcba 765 43210 k control encoded word ( ? ) encoded word (+) abcdei fghj abcdei fghj k28.0 000 11100 1 001111 0100 110000 1011 k28.1 001 11100 1 001111 1001 110000 0110 k28.2 010 11100 1 001111 0101 110000 1010 k28.3 011 11100 1 001111 0011 110000 1100 k28.4 100 11100 1 001111 0010 110000 1101 k28.5 101 11100 1 001111 1010 110000 0101 k28.6 110 11100 1 001111 0110 110000 1001 k28.7 111 11100 1 001111 1000 110000 0111 k23.7 111 10111 1 111010 1000 000101 0111 k27.7 111 11011 1 110110 1000 001001 0111 k29.7 111 11101 1 101110 1000 010001 0111 k30.7 111 11110 1 011110 1000 100001 0111
agere systems inc. 31 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) 8b/10b link alignment setup in order to align the receive channels in 8b/10b mode, the following procedure should be followed: 1. enable 8b/10b mode for all eight channels by setting the en10bit found at control register address 0xe0 (bit # 1). 2. enable the encomma bits for all used channels at control register address 0x300e3 (one bit per channel). 3. put all of the streams to be aligned, including disabled streams, into their required alignment mode. 4. transmit at least 100 packets across each link to be aligned. 5. write a 0x01 to the fifo alignment resync register bits as required in control register 0x30017 or 0x30018. pointer mover block (backplane fpga) the pointer mover maps incoming frames to the line framing that is supplied by the fpga logic. there is a sepa- rate pointer mover for the two stm macro slices, a and b, each of which handles up to one sts-48 (four chan- nels), but there is only one line frame pulse imput (line_fp) shared by both pointer mover blocks. the k1/k2 bytes and h1-ss bits are also passed through to the pointer generator so that the fpga can receive them. the pointer mover handles both concatenations inside the sts-12, and to other sts-12s inside the core. the pointer mover block can correctly process any length of concatenation of sts frames (multiple of three) as long as it begins on an sts-3 boundary (i.e., sts-1 number one, four, seven, ten, etc.) and is contained within the smaller of sts-3, 12, or 48. see details in table 7. table 7. valid starting positions for an sts-mc note: yes = sts-mc spe can start in that sts-1. no = sts-mc spe cannot start in that sts-1. ? = yes or no, depending on the particular value of m. sts-1 number sts-3cspe sts-6cspe sts-9cspe sts-12cspe sts-15cspe sts-18c to sts-48c spes 1 yes yes yes yes yes yes 4 yes yes yes no yes ? 7 yes yes no no yes ? 10 yes no no no yes ? 13 yes yes yes yes yes ? 16 yes yes yes no yes ? 19 yes yes no no yes ? 22 yes no no no yes ? 25 yes yes yes yes yes ? 28 yes yes yes no yes ? 31 yes yes no no yes ? 34 yes no no no yes no 37 yes yes yes yes no no 40 yes yes yes no no no 43 yes yes no no no no 46 yes no no no no no
32 32 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) pointer interpreter state machine. the pointer inter- preter ? s highest priority is to maintain accurate data flow (i.e., valid spe only) into the elastic store. this will ensure that any errors in the pointer value will be cor- rected by a standard, fully sonet compliant, pointer interpreter without any data hits. this means that error checking for increment, decrement, and new data flag (ndf) (i.e., 8 of 10) is maintained in order to ensure accurate data flow. a single valid pointer (i.e., 0 ? 782) that differs from the current pointer will be ignored. two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the j1 location to the latest pointer value (the generator will then produce an ndf). this block is designed to handle single bit errors without affecting data flow or changing state. the pointer interpreter has only three states (norm, ais, and conc). norm state will begin whenever two consecutive norm pointers are received. if two con- secutive norm pointers that both differ from the cur- rent offset are received, then the current offset will be reset to the last received norm pointer. when the pointer interpreter changes its offset, it causes the pointer generator to receive a j1 value in a new posi- tion. when the pointer generator gets an unexpected j1, it resets its offset value to the new location and declares an ndf. the interpreter is only looking for two consecutive pointers that are different from the current value. these two consecutive norm pointers do not have to have the same value. for example, if the cur- rent pointer is ten and a norm pointer with offset of 15 and a second norm pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. the receipt of two consecutive conc pointers causes conc state to be entered. once in this state, offset values from the head of the concate- nation chain are used to determine the location of the sts spe for each sts in the chain. two consecutive ais pointers cause the ais state to occur. any two con- secutive normal or concatenation pointers will end this ais state. this state will cause the data leaving the pointer generator to be overwritten with 0xff. 5-8589 (f) figure 13. pointer mover state machine pointer generator. the pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. the generator also creates offset pointers based on the location of the j1 byte as indicated by the pointer interpreter. the generator will signal ndfs when the interpreter signals that it is com- ing out of ais state. the pointer generator resets the pointer value and generates ndf every time a byte marked j1 is read from the elastic store that doesn ? t match the previous offset. increment and decrement signals from the pointer interpreter are latched once per frame on either the f1 or e2 byte times (depending on collisions); this ensures constant values during the h1 through h3 times. the choice of which byte time to do the latching on is made once when the relative frame phases (i.e., received and system) are determined. this latch point is then stable unless the relative framing changes and the received h byte times collide with the system f1 or e2 times, in which case the latch point would be switched to the collision-free byte time. there is no restriction on how many or how often incre- ments and decrements are processed. any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. the responsibility for meeting the sonet criteria for maximum frequency of pointer adjustments is left to an upstream pointer processor. when the interpreter signals an ais state, the genera- tor will immediately begin sending out 0xff in place of data and h1, h2, h3. this will continue until the inter- preter returns to norm or conc (pointer mover state machine) states and a j1 byte is received. norm conc ais 2 x c o n c 2 x n o r m 2 x n o r m 2 x a i s 2 x conc 2 x ais
agere systems inc. 33 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) receive bypass options and fpga interface not all of the blocks in the receive direction are required to be used. the following bypass options are valid in the receive (backplane fpga) direction: stm pointer mover bypass: ? in this mode, data from the alignment fifos is transferred to the fpga logic. all channels are synchronous to the fpga_sysclk signals driven to the fpga logic, as is also the case when the pointer mover is not bypassed. during bypass spe, c1j1, and data parity signals are not valid. when the pointer mover is bypassed, a frame pulse from aligned channels (doutxy_fp) is pro- vided by the embedded core. when the pointer mover is used, the fpga logic provides the frame pulse on the line_fp signal. stm pointer mover and alignment fifo bypass: ? in this mode, data from the framer block is transferred to the fpga logic. all channels supply data and frame pulses synchronous with their individual recovered clock (cdr_clk_xy) per channel. during bypass, spe, c1j1, and data parity signals are not valid. 8b/10b alignment fifo bypass: ? when in 8b/10b mode, the data from the 8b/10b decoder is passed to the fpga logic if the align- ment fifo is bypassed. all channels suppply data and commadet signals synchronous with their individual recovered clock (cdr_clk_xy) per chan- nel. when not bypassed, the 8b/10b alignment clock provides all channels and a commadet signal synchronous to the fpga_sysclk signal to the fpga logic. powerdown mode powerdown mode will be entered when the corre- sponding channel is disabled. channels can be inde- pendently enabled or disabled under software control. parallel data bus output enable and toh serial data output enable signals are made available to the fpga logic. the hsi macrocell ? s corresponding channel is also powered down. the device will power up with all eight channels in powerdown mode. stm redundancy and protection switching the ort8850 supports sts-12/sts-48 redundancy by either software or hardware control for protection switching applications. for the transmitter mode, no additional functionality is required for redundant opera- tion. for receiving data, sts-12 and sts-48 data redundancy can be implemented within the same device, while sts-192 and above data stream requires multiple ort8850 devices to support redundancy. in sts-12 mode, the channel a receive data bus port is used for both channel a and channel b. similarly, the channel c receive data bus port is used for both chan- nel c and channel d. channel b and channel d become the redundant channels. the channel b and channel d receive data bus ports are unused. soft reg- isters provide independent control to the protection switching muxes for both parallel data ports and serial toh data ports. when direct hardware control for pro- tection switching is needed, external protection switch pins are available for channels a and b, and also chan- nels c and d. the external protection switch pins only support parallel spe/toh data protection switching, but not the serial toh data. these protection switching pins are listed in table 28 as prot_switch_xx. for sts-48 redundancy, the two 4-channel macro blocks are both used: four channels for work and four channels for protect. the switching between work and protect is extended to either be between four-channel macros or between the a/b and c/d channels within both macros. in sts-192 mode, multiple independent devices are required to work and protect for redundancy. parallel and serial port output pins on the fpga side should be 3-stated as the basis for supporting redundancy. the existing local bus enable signals at the cic can be used as 3-state controls for fpga data bus if needed, which can be easily accessed by software control. users can also create their own protection switch 3-state enable signals either in fpga logic or external to the device, depending on the specific application. the stm protection switch circuitry is not available in 8b/10b mode or stm pointer mover and alignment fifo bypass mode. it is available when only the pointer mover is bypassed.
34 34 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc backplane transceiver core detailed description (continued) lvds protection switching each serdes link sends and receives data on two lvds buffers. for example, data is transmitted through serdes aa to tx_b[0] as the work link and tx_c[0] as the protect link. data is received through two lvds buffers and a switch is provided to select between the work and protect buffer. the signal lvds_prot_aa pro- vided in the fpga logic selects between the work link buffer (rx_b[0]) and the protect link buffer (rx_c[0]). these signals select the protect link when high and the work link when low. lvds protection switching can be used in either 8b/ 10b mode or when using stm. stm redundancy and protection switching discussed in the previous section can only be used with the stm. lvds protection switching can also be switched using software control. consult the memory map in table 10 for more informa- tion. rapidio interface to pi-sched overview the ort8850 includes three byte-wide, full-duplex ddr rapidio interfaces running at up to 311 mhz (622 mbits/s) per line for a total of 5.0 gbits/s for each interface. each input and output interface includes byte-wide data, one control signal (such as start-of- cell), and one clock signal. one of the three rapidio interfaces is always available. the other two rapidio interface are available only if the eight cdr channels are not being used. one function of the ort8850 is to interface with the protocol independent scheduler (pi-sched) device on a port card. the pi-sched ic is part of the high-speed switching (hssw) family of devices. it offers a highly integrated, innovative, and complete vlsi solution for implementing the scheduling and buffer management functionality of a cell (e.g., atm) or packet (e.g., ip) switching system port at oc-48c. the rapidio in the ort8850 will support the dedi- cated receive and transmit interfaces for off-chip com- munication. both interfaces drive or receive off-chip through lvds i/o pads. the lvds i/os are fully termi- nated on-chip to allow for driving high-speed parallel backplanes at speeds up to 311 mhz. internally, each 8-bit rapidio interface is connected to a 32-bit inter- face which is single-edge clocked and connected to the fpga logic array. for example, byte-wide 311 mhz ddr data is converted to 155 mhz 32-bit wide data at the fpga interface. the primary task of the rapidio is to process bytes of data known as octets transmitted as a group known as a cell. an octet is described as 8 bits found within a cell. once the first octet of a cell is received, subse- quent octets are part of an uninterrupted data stream until the entire cell has been received. the beginning of the next cell will determine the boundary of the previ- ous cell. the beginning of a cell is indicated by a pulse on the start-of-cell, soc signal. the soc signal always accompanies the cell data. at the i/o boundary, cell data is present on an 8-bit data bus with the first octet and soc aligned with the rising edge of the clock. at the fpga end, cell data is present on a 32-bit data bus. thus, the rapidio is used to translate between the 32-bit data bus and the 8-bit i/o data bus while monitoring the integrity of the cells being processed. receive cell interface the receive interface performs demultiplexing from four sequential octets of eight pairs of lvds pins using both edges of the high-speed clock onto internal 32-bit buses at the low-speed clock. the interface includes the following signals (see figure 14): one lvds clock pair running at 120 mhz ? 311 mhz. its relationship is intended to be in the eye of the receive cell data. one lvds start-of-cell pair, which indicates that word 0 of a data cell is on the receive data port. eight lvds data pairs, double-edge clocked by the lvds clock. the eight lvds data pairs are double-edge clocked by the lvds receive clock (rxclk). the rxclk is aligned to the center of the eye of the received data and start-of-cell (rxd and rxsoc). to achieve opti- mal timing margin, the receiver is required to maintain this alignment. the rapidio interface requires that the soc spacing is an integer multiple of two clock cycles for proper operation and that socs occur only on the rising edge of the receive clock (rxclk).
agere systems inc. 35 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc rapidio interface to pi-sched (continued) 0676 figure 14. rapidio receive cell interface octets and start of cell cells will be transmitted on the high-speed lvds inputs as octets. the first octet o0 (consisting of d0_0, d1_0 . . . d7_0) will be present on bits 31:24 on the low-speed 32-bit fpga bus. similarly, octet o1 (consist- ing of d0_1, 1_1 . . . d7_1) will be present on bits 23:16 on the 32-bit bus. thus, octets will always be transmitted from first octet to last. the minimum number of octets present on the high-speed ports should always be divisible by 4, evenly representing the relationship with the 32-bit core of the asic interface. the start-of-cell signal is always aligned with the first octet of each cell. once the first octet of a cell is received, subsequent octets are part of an uninterrupted data stream until the entire cell has been received. the number of octets in a cell is determined by the register bits ocellsize. the rapidio can support varying minimum cell sizes from four octets up to 124 in increments of 4. the rapidio is programmed with the cell size by writing to the ocellsize register via the micro- processor interface. if the transmitted cell size is less than the programmed cell size, a violation occurs and the irxsocviol flag is active. this flag can be ignored if a given minimum cell size is not needed. d clk q rxclk rxsoc d ck q zrxd_7 zrxd_23 zrxd_31 zrxd_15 wrxclk (133 mhz) to fpga 133 mhz clock domain 266 mhz clock domain input repeated 7 times (one for each of rxd[1:7]) dq zrxsoc dq dq dq rxd[7] rxd[0] zrxd_15 d clk q data capture shift registers d ck q d ck q d ck q d ck q d ck q d ck q d ck q d ck q
36 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc rapidio interface to pi-sched (continued) 0677 figure 15. rapidio transmit cell interface transmit cell interface the transmit interface performs multiplexing of 32 bits of low-speed data onto four sequential octets of eight pairs of lvds signal pins using both edges of a high-speed clock. the transmitter module consists of the following ten lvds signal pairs (see figure 15): eight lvds data pairs (txd), double-edge clocked by the lvds clock txclk. the data pairs carry biphase data at 120 mhz ? 311 mhz. one start-of-cell lvds pair that indicates that octet 0 of a data cell is on txd. the transitions of this signal are at 90 degrees also with the crossing points of the lvds clock (txclk). one lvds clock pair output txclk operating at 120 mhz ? 311 mhz. its relationship is intended to be exactly in 90 degree phase with the transitions of txd data and txsoc. the high-speed data outputs (txd[0:7]) as well as the start-of-cell signal txsoc are generated as a result of the positive edge of pfclk. this is accomplished by multiplexing between the even and odd bytes of the data at a 1/2 pfclk rate. pfclk is derived from the internal pll and operates at 4x the base frequency or between 240 mhz and 284 mhz. the pfclk is expected to have a duty cycle of 47% to 53% with no more than 150 ps of jitter. the duty cycle of pfclk will directly affect the accuracy of the high-speed clock and its ability to maintain the eye of the data. the 90 degree phase shift of the output clock puts txclk in the eye of the data. common transmit fifo even byte odd byte even byte utxd [31:0] utxsoc wutxclk (60 mhz ? 146 mhz) output port clock alignment mux output port soc alignment mux fpga i/f pfclk (4x output clock from pll) 32 to 8 input soc register soc txsoc (240 mhz ? 584 mhz) off-chip interface pll positive- output port data alignment muxes mux controller txclk txd[7:0] odd byte output port data alignment muxes edge flops negative- edge flops
agere systems inc. 37 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc rapidio interface to pi-sched (continued) table 8. rapidio signals to/from fpga interface name (all end with _a, _b, or _c depending on channel) from fpga to fpga description receive cell interface zrxd<31:0> ? 32 32-bit data from the receive module. the bus contains four octets and reflects data received via the high-speed rxd data bus. zrxsoc ? 1 indicates the presence of the first octet of a new cell within the first 32-bit data word on the bus rxd in bit positions [31:24]. zrxsocviol ? 1 indicates a minimum cell violation within the receive module. this signal will transition active-high coincident with rxsoc. an active state signals the new cell overran the previous cell, and the previous cell is in violation of the minimum cell size. zrxalnviol ? 1 signals an alignment error. an active state signals rxsoc was captured on a negative rxclk edge. the violation condition on this signal will stay high for a single wrxclk_[chan]_fpga cycle coincident with rxsoc. zclkstat ?? indicates the loss or absence of a clock on the lvds clock (rxclk). this signal will be present for the duration of the absence of the clock, following a period to validate its absence. csysenb 1 ? system cell processing enable. after reset is released, drive this signal high when the rapidio is ready to transmit cells. this signal should be active after all control signals into the rapidio are stable. rstn_rx 1 ? synchronous reset for all memory elements clocked by wrxclk_[chan]_fpga (derived from pll). wrxclk_[chan]_fpga ? 1 derived from high-speed lvds clock rxclk (rxclk/2). transmit cell interface utxd[31:0] 32 ? transmit data bs containing four octets synchronized with the rising edge of the 60 mhz ? 146 mhz wutxclk_fpga (derived from pll) is clocked into the transmit fifo within the rapidio . utxsoc 1 ? start of cell, originating within core, synchronized with the ris- ing edge of wutxclk_fpga into the transmit fifo. indicates the first data word on txd bus includes the first octet of a new cell in bit positions [31:24]. rstn_utx 1 ? synchronous reset for all memory elements in the wutxclk domain. utxtristn 1 ? output 3-state enable (active-low). when active, the txd, txsoc, and txclk lvds drivers are 3-stated. 0: 3-state txd, txsoc and txclk drivers. 1: normal operation. fpga interface clocks (common to all channels) wutxclk_fpga ? 1 one x core clock generated from an internal pll circuit. syn- chronous to utxd and utxsoc data inputs. halfclk_fpga ? 1 1/2 x main pll output clock. phase-aligned with pfclk. nom- inal frequency = 30 mhz to 73 mhz. duty cycle spec = 47%/ 53%.
38 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc rapidio interface to pi-sched (continued) table 9. signals used as register bits memory map definition of register types there are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. there are no mixed registers in the chip. this means that all bits of a particular register (particular address) are structurally the same. all of these registers are accessed via the fpga system bus which, in turn, can be accessed by the mpi block or through fpga logic. register bit(s) description oshlbenb used during the internal built-in self-test mode. indicates that the single-ended versions of the transmit module outputs should be looped back into the single-ended inputs of the receive module. oshlenb = 0: no loopback. oshlenb = 1: loopback. ocellsize[4:0] this value indicates the minimum cell size and will be used to detect cell underrun errors. this value should be set and stable prior to initialization of operation and stable thereafter. otestenb enables the internal self-test of the rapidio block. two loopback paths exist during test, inter- nal and external. during both tests, data is passed through all modules and verified. itestdone indicates the completion of the internal test. only valid during a test when otestenb is high. itestdone = 0: test running. itestdone = 1: test complete. itestpass indicates the success of the internal test. this signal is valid only when itestdone is high. itestpass = 0: test failed. itestpass = 1: test passed. tristn active-low. 3-state override for transmit outputs. this signal is ignored during reset, but takes priority over all 3-state control signals when active.
agere systems inc. 39 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 10. structural register elements registers access and general description the memory map comprises three address blocks: generic register block: id, revision, scratch pad, lock, fifo alignment, and reset registers. device register block: control and status bits, common to the four channels in each of the two quad interfaces. channel register blocks: each of the four channels in both quads have an address block. the four address blocks in both quads have the same structure, with a constant address offset between channel register blocks. all registers are write-protected by the lock register, except for the scratch pad register. the lock register is a 16-bit read/write register. write access is given to registers only when the key value 0x0580 is present in the lock register. an error flag will be set upon detecting a write access when write permission is denied. the default value is 0x0000. after powerup reset or soft reset, unused register bits will be read as zeros. unused address locations are also read as zeros. write-only register bits will be read as zeros. the detailed information on register access and func- tion are described on the tables, memory map, and memory map bit description. a memory map is included in table 11, followed by detailed descriptions in table 11. these tables list only the memory map for the core registers of the ort8850 device. the remaining fpga registers can be found in the series 4 data sheet. element register description sreg status register a status register is read only, and, as the name implies, is used to convey the status information of a particular element or function of the ort8850 core. the reset value of an sreg is really the reset value of the particular element or function that is being read. in some cases, an sreg is really a fixed value; an example of which is the fixed id and revision registers. creg control register a control register is read and writable memory element inside core control. the value of a creg will always be the value written to it. events inside the ort8850 core cannot affect creg value. the only exception is a soft reset, in which case the creg will return to its default value. preg pulse register each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when a value of one is written to it. this means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. a pulse register will always have a read value of 0. iareg interrupt alarm register each bit of an interrupt alarm register is an event latch. when a particular event is pro- duced in the ort8850 core, its occurrence is latched by its associated iareg bit. to clear a particular iareg bit, a value of one must be written to it. in the ort8850 core, all isreg reset values are 0. isreg interrupt status register each bit of an interrupt status register is physically the logical-or function. it is a con- solidation of lower-level interrupt alarms and/or isreg bits from other registers. a direct result of the fact that each bit of the isreg is a logical-or function means that it will have a read value of one if any of the consolidation signals are of value one, and will be of value 0 if and only if all consolidation signals are of value 0. in the ort8850 core, all isreg default values are 0. ereg interrupt enable register each bit of a status register or alarm register has an associated enable bit. if this bit is set to value one, then the event is allowed to propagate to the next higher level of con- solidation. if this bit is set to zero, then the associated iareg or isreg bit can still be asserted but an alarm will not propagate to the next higher level. an interrupt enable bit is an interrupt mask bit when it is set to value 0.
40 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) this table is constructed to show the correct values when read and written via the system bus mpi interface. when using this table while interfacing with the system bus user logic master interface, the data values will need to be byte flipped. this is due to the opposite orientation of the mpi and master interface bus ordering. more information on this can be found in the mpi/system bus application note (ap01-032ncip). table 11. memory map (this table resides at memory offset 0x30000 in the ort8850.) addr [7:0] register type db7 db6 db5 db4 db3 db2 db1 db0 msb reset value [7:0] comment 00 sreg fixed rev [0:7] 05 generic register block 01 sreg fixed id lsb [0:7] 80 02 sreg fixed id msb [0:7] 80 03 creg scratch pad [0:7] 00 04 creg lockreg msb [0:7] 00 05 creg lockreg lsb [0:7] 00 06 preg ??? ? ??? global reset comman d na device register block 08 creg ??? ? rx toh frame ? and ? rx toh clk enable ? hiz control ext prot sw en ?? lvds lpbk control (cdr only) 00 device reg. blk - rx 09 creg parallel port output mux select for ch#7 parallel port output mux select for ch#5 serial port output mux select for ch#7 serial port output mux select for ch#5 parallel port output mux select for ch#3 parallel port output mux select for ch#1 serial port output mux select for ch#3 serial port output mux select for ch#1 ff (4 ch was 0f) 0a creg ??? fifo aligner threshold value (min) [0:4] 40 0b creg ??? fifo aligner threshold value (max) [0:4] a8 0c creg ? scram- bler/ descra- mbler control input/ output parallel bus parity control line lpbk control number of consecutive a1 a2 errors to generate [0:3] 06 device reg blk - tx 0d creg a1 error insert value [0:7] 00 0e creg a2 error insert value [0:7] 00 0f creg transmitter b1 error insert mask [0:7] 00
agere systems inc. 41 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 11. memory map (continued) addr [7:0] register type db7 db6 db5 db4 db3 db2 db1 db0 msb reset value [7:0] comment 10 isreg ??? per device int ch 4 int ch 3 int ch 2 int ch 1 int 00 top-level interrupts 11 iereg ??? enable/mask register [0:4] 00 12 iareg ? ? ???? write to locked register error flag frame offset error flag 00 13 iereg ? ? ???? enable/mask register [6:7] 00 14 isreg ???? ch 8 int ch 7 int ch 6 int ch 5 int 00 15 iereg ???? enable/mask register [0:3] 00 16 creg ???? stm-a mode control stm-a mode control stm-b mode control stm-b mode control 0x00 ? 17 creg stm a stream a resync. stm a stream b resync stm a stream c resync stm a stream d resync stm b stream a resync stm b stream b resync stm b stream c resync stm b stream d resync 00 ? 18 creg ? stm a and b resync (all 8 streams aa to bd) stm a resync (all 4 streams aa, ab, ac and ad) stm b resync (all 4 streams ba, bb, bc and bd) twins aa resync (streams aa and ba) twins bb resync (streams ab and bb) twins cc resync (streams ac and bc) twins dd resync (streams ad and bd) 00 ? channel register block 20, 38, 50, 68, 80, 98, b0, c8 creg hi-z control of toh data output hi-z control of parallel output bus channel enable/ disable control parallel output bus parity err ins cmd rx k1/k2 source select toh serial output port par err ins cmd force ais-l control rx behavior in lof 80 rx control signals 21, 39, 51, 69, 81, 99, b1, c9 creg tx mode of operatio n tx e1 f1 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12 source select tx d11 source select tx d10 source select tx d9 source select 00 tx control signals 22, 3a, 52, 6a, 82, 9a, b2, ca creg tx d8 source select tx d7 source select tx d6 source select tx d5 source select tx d4 source select tx d3 source select tx d2 source select tx d1 source select 00 23, 3b, 53, 6b, 83, 9b, b3, cb creg ???? disable a1/a2 insert disable b1 insert b1 error insert comman d a1 a2 error ins comman d 00
42 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 11. memory map (continued) * the fifo aligner threshold error flag is only valid if a fifo out of sync error flag is also present. addr [7:0] register type db7 db6 db5 db4 db3 db2 db1 db0 msb reset value [7:0] comment 24, 3c, 54, 6c, 84, 9c, b4, cc sreg ???? concat indication 12 concat indication 9 concat indication 6 concat indication 3 na per sts#1 cos flag 25, 3d, 55, 6d, 85, 9d, b5, cd sreg concat indication 11 concat indication 8 concat indication 5 concat indication 2 concat indication 10 concat indication 7 concat indication 4 concat indication 1 na 26, 3e, 56, 6e, 86, 9e, b6, ce isreg ????? elastic store overflow flag ais-p flag per sts-12 alarm flag 00 per channel interrupt consolidation 27, 3f, 57, 6f, 87, 9f, b7, cf iereg ????? enable/mask register [0:3] 00 28, 40, 58, 70, 88, a0, b8, d0 iareg ? fifo (out of sync) error flag toh serial input port parity error flag input parallel bus parity error flag lvds link b1 parity error flag lof flag receiver internal path parity error flag fifo* aligner threshold error flag 00 per sts-12 interrupt flags 29, 41, 59, 71, 89, a1 b9, d1 iereg ?? enable/mask register [0:5] 00
agere systems inc. 43 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 11. memory map (continued) addr [7:0] register type db7 db6 db5 db4 db3 db2 db1 db0 msb reset value [7:0] comments 2a, 42, 5a, 72, 8a, a2, ba, d2 iareg ???? ais interrupt flags 12 ais interrupt flag 9 ais interrupt flags 6 ais interrupt flags 3 00 per sts-1 interrupt flags 2b, 43, 5b, 73, 8b, a3, bb, d3 iareg ais interrupt flag 11 ais interrupt flag 8 ais interrupt flag 5 ais interrupt flag 2 ais interrupt flag 10 ais interrupt flag 7 ais interrupt flag 4 ais interrupt flag 1 00 2c, 44, 5c, 74, 8c, a4, bc, d4 iereg ???? enable/ mask ais interrupt flags 12 enable/ mask ais interrupt flag 9 enable/ mask ais interrupt flags 6 enable/ mask ais interrupt flags 3 00 2d, 45, 5d, 75, 8d, a5, bd, d5 iereg enable/ mask ais interrupt flag 11 enable/ mask ais interrupt flag 8 enable/ mask ais interrupt flag 5 enable/ mask ais interrupt flag 2 enable/ mask ais interrupt flag 10 enable/ mask ais interrupt flag 7 enable/ mask ais interrupt flag 4 enable/ mask ais interrupt flag 1 00 2e, 46, 5e, 76, 8e, a6, be, d6 iareg ???? es overflow flags 12 es overflow flag 9 es overflow flags 6 es overflow flags 3 00 2f, 47, 5f, 77, 8f, a7, bf, d7 iareg es overflow flag 11 es overflow flag 8 es overflow flag 5 es overflow flag 2 es overflow flag 10 es overflow flag 7 es overflow flag 4 es overflow flag 1 00 30, 48, 60, 78, 90, a8, c0, d8 iereg ???? enable/ mask es overflow flags 12 enable/ mask es overflow flag 9 enable/ mask es overflow flags 6 enable/ mask es overflow flags 3 00 ? 31, 49, 61, 79, 91, a9, c1, d9 iereg enable/ mask es overflow flag 11 enable/ mask es overflow flag 8 enable/ mask es overflow flag 5 enable/ mask es overflow flag 2 enable/ mask es overflow flag 10 enable/ mask es overflow flag 7 enable/ mask es overflow flag 4 enable/ mask es overflow flag 1 00 ?
44 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 11. memory map (continued) addr [7:0] register type db7 db6 db5 db4 db3 db2 db1 db0 msb reset value [7:0] comments 32, 4a, 62, 7a, 92, aa, c2, da counter overflow lvds link b1 bip-8 parity error counter 00 binning 33, 4b, 63, 7b, 93, ab, c3, db counter overflow lof counter 00 34, 4c, 64, 7c, 94, ac, c4, dc counter overflow a1 a2 frame error counter 00 35, 4d, 65, 7d, 95, ad, c5, dd creg reserved ?? fifo depth register 0x0c ? 36, 4e, 66, 7e, 96, ae, c6, de counter sampler phase error count 00 ? 37, 4f, 67, 7f, 97, af, c7, df creg ?? framer disable sync control lvds redun- dant select bypass alignment fifo + pointer mover bypass pointer mover 00 ? cdr specific registers e0 creg tst mode bypass loop bken tst phase ? en10bit shim mode ?? e3 creg encomma[0:7] ?? pi-sched registers f0 creg ? rapidio (shim) loopback enable opimode (reserved) ocellsize[3:7] ?? f1 sreg ? ? ? ??? itestdo ne itest pass 0 ? f2 creg ? ? ? ??? ibypass otest enb ??
agere systems inc. 45 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions bit/register name(s) bit/ register location (hex) register type reset value (hex) description fixed rev [0:7] fixed id lsb [0:7] fixed id msb [7:0] 00 [0:7] 01 [0:7] 02 [0:7] sreg 05 80 80 na scratch pad [0:7] 03 [0:7] creg 00 the scratch pad has no function and is not used anywhere in the core. however, this register can be written to and read from. lockreg msb [0:7] lockreg lsb [0:7] 04 [0:7] 05 [0:7] creg 00 00 in order to write to registers in memory locations 06~7f, lockreg msb and lockreg lsb must be respectively set to the values of 05 and 80. if the msb and lsb lockreg values are not set to {05, 80}, then any values written to the registers in memory loca- tions 06~7f will be ignored. after reset (both hard and soft), the core is in a write locked mode. the core needs to be unlocked before it can be written to. also note that the scratch pad register (03) can always be writ- ten to as it is unaffected by write lock mode. global reset com- mand 06 [0] preg na the global reset command is accessed via the pulse register in memory address 06. the global reset command is a soft (soft- ware initiated) reset. nevertheless, the global reset command will have the exact reset effect as a hard (rst_n pin) reset. device register blocks lvds lpbk control 08 [0] creg 0 ext prot sw en 08 [3] creg 0 ? rx toh frame ? and ? rx toh clk enable ? hiz control 08 [4] creg 0 cdr 0 no loopback. 1 lvds loopback, transmit to receive on. serieal data is looped back to the rx serial input. ext port sw en lvds protection switching 0- mux is controlled by software (1 control bit per mux) reg 09 . - output buffers ? enables are controlled by software (1 control bit per chan- nel) reg 20, 38, 50, 68, 80, 98, b0, c8. 1 mux is controlled by hardware pins. lvds_prot_switch_[aa,ab,ac,ad,ba,bb,bc,bd] 0 toh_ck_fp_en = 0, can be used to 3-state rx_toh_ck_en and rx_toh_fp signals. 1 function mode.
46 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description serial port output mux select for ch#1 serial port output mux select for ch#3 parallel port output mux select for ch#1 parallel port output mux select for ch#3 serial port output mux select for ch#5 parallel port output mux select for ch#7 serial port output mux select for ch#5 parallel port output mux select for ch#7 09 [0] 09 [1] 09 [2] 09 [3] 09 [4] 09 [5] 09 [6] 09 [7] creg 1 1 1 1 fifo aligner threshold value (min) default = 2 fifo aligner threshold value (max) default = 15 0a [0:4] 0b [0:4] creg 40 a8 these are the minimum and maximum thresholds values for the per channel receive direction align- ment fifos. if and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event ? fifo aligner threshold error ? will be generated for that channel and latched as a ? fifo aligner threshold error flag ? in the respective per sts-12 interrupt alarm register. the allowable range for minimum threshold values is 1 to 23. the allowable range for maximum threshold values is 0 to 22. note that the minimum and maximum fifo aligner threshold values apply to all four channels. number of consecutive a1 a2 errors to generate [0:3] a1 error insert value [0:7] a2 error insert value [0:7] 0c [0:3] 0d [0:7] 0e [0:7] creg 00 00 00 these three per device control signals are used in conjunction with the per channel ? a1 a2 error insert command ? control bits to force a1 a2 errors in the transmit direction. if a particular channel ? s ? a1 a2 error insert com- mand ? control bit is set to the value 1 then the ? a1 and a2 error insert values ? will be inserted into that channels respective a1 and a2 bytes. the number of consecutive frames to be corrupted is deter- mined by the ? number of consecutive a1 a2 errors to generate[0:3] ? control bits. the error insertion is based on a rising edge detec- tor. as such the control must be set to value 0 before trying to initiate a second a1 a2 corruption. backplane side loop- back control 0c [4] creg 0 serial port output mux 0 toh output is multiplexed to next channel. 1 toh output is multiplexed to same channel. parallel port output 0 parallel output data bus is multiplexed to next channel. 1 parallel output data bus is multiplexed to same channel 0 no loopback. 1 rx to tx loopback on backplane side. serial input is run through serdes and looped back in parallel to serdes and out serial.
agere systems inc. 47 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description input/output parallel bus parity control 0c [5] creg 1 scrambler/descrambler control 0c [6] creg 1 transmit b1 error insert mask [0:7] 0f [0:7] creg 00 ch 1 int ch 2 int ch 3 int ch 4 int per device int enable/mask register for ch 1-4 + device[4:0] ch 5 int ch 6 int ch 7 int ch 8 int enable/mask register for ch 5-8 [0:3] 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [0:4] 14 [0] 14 [1] 14 [2] 14 [3] 15 [0:3] isreg isreg isreg isreg isreg iereg isreg isreg isreg isreg iereg 0 0 0 0 0 0 0 0 0 0 0 consolidation interrupts. 1 = interrupt, 0 = no interrupt. frame offset error flag write to locked register error flag enable/mask register [0:1] 12 [0] 12 [1] 13 [0:1] iareg iareg iereg 0 0 0 if in the receive direction the phase offset between any two channels exceeds 17 bytes, then a frame offset error event will be issued. this condition is continuously monitored. if the core memory map has not been unlocked (by writing to the lock registers), and any address other than the lock- reg registers or scratch pad register is written to, then a ? write to locked register ? event will be generated. stm a mode control stm b mode control 16 [2:3] 16 [0:1] creg creg 0 0 00 - quad sts-12 or sts-48. 01 - quad sts-3. 10 - quad sts-1. 00 - quad sts-12 or sts-48. 01 - quad sts-3. 10 - quad sts-1. individual alignment resync register 17 [0:7] creg 0 write 1 to resync stream. group alignment resync register 18 [0:7] creg 0 write 1 to resync selected grouping. 0 even parity. 1 odd parity. 0 no rx direction, descramble / tx direction scramble. 1 in rx direction, descramble channel after sonet frame recov- ery. in tx direction, scramble data just before parallel-to-serial con- version. 0 no error insertion. 1 invert corresponding bit in b1 byte.
48 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description channel register blocks rx behavior in lof force ais-l control 20, 38, 50, 68, 80, 98, b0, c8 [0] 20, 38, 50, 68, 80, 98, b0, c8 [1] ? 1 0 toh serial output port par err ins cmd 20, 38, 50, 68, 80, 98, b0, c8 [2] ? 0 rx k1/k2 source select 20, 38, 50, 68, 80, 98, b0, c8 [3] ? 0 parallel output bus parity err ins cmd 20, 38, 50, 68, 80, 98, b0, c8 [4] ? 0 channel enable/disable control hi-z control of parallel output bus hi-z control of toh data output 20, 38, 50, 68, 80, 98, b0, c8 [5] 20, 38, 50, 68, 80, 98, b0, c8 [6] 20, 38, 50, 68, 80, 98, b0, c8 [7] creg creg creg 0 0 0 rx behavior in log 0 when rx direction oof occurs, do not insert ais-l. 1 when rx direction oof occurs, insert ais-l. force ais-l control 0 do not force ais-l. 1 force ais-l. 0 do not insert a parity error. 1 insert parity error in parity bit of receive toh serial output for as long as this bit is set. 0 set receive direction k2 k2 bytes to 0. 1 pass receive direction k1 k2 though pointer mover. 0 do not insert parity error. 1 insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set. channel enable / dis- able control 0 power down cdr channels (pwr_dn_a/b/c/ d_n=0). toh_en_a(or b, c, d)=0, and douta(or b, c, d)=0, can be used to 3-state out- put buses. 1 functional mode. hi-z control of parallel output bus 0 douta(or b, c, d) _en=0, can be used to 3-state output bus. 1 functional mode. hi-z control of toh data out- put 0 toh_en_a(or b, c, d)=0, can be used to 3-state toh output lines.
agere systems inc. 49 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description tx mode of operation tx e1 f2 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12~d9 source select tx d8~d1 source select 21, 39, 51, 69, 81, 99, b1, c9 [7] 21, 39, 51, 69, 81, 99, b1, c9 [6] 21, 39, 51, 69, 81, 99, b1, c9 [5] 21, 39, 51, 69, 81, 99, b1,c9 [4:0] 22, 3a, 52, 6a, 82, 9a, b2, ca [7:0] creg creg creg creg creg 0 0 0 0 00 a1 a2 error insert command b1 error insert command disable b1 insert disable a1 insert 23, 3b, 53, 6b, 83, 9b, b3, cb [0] 23, 3b, 53, 6b, 83, 9b, b3, cb [1] 23, 3b, 53, 6b, 83, 9b, b3, cb [2] 23, 3b, 53, 6b, 83, 9b, b3, cb [3] creg creg 0 0 concat indication 12, 9, 6, 3 concat indication 11, 8, 5, 2, 10, 7, 4, 1 24, 3c, 54, 6c, 84, 9c, b4, cc [0:3] 25, 3d, 55, 6d, 85, 9d, b5, cd [0:7] sreg sreg 0 0 the value 1 in any bit location indicates that sts# is in concat mode. a 0 indicates that the sts in not in concat mode, or is the head of a concat group. tx mode of operation: other registers: 0 insert toh from serial ports on fpga interface. 1 pass through all toh of parallel stream. 0 insert toh from serial ports on fpga interface. 1 pass through that particular toh byte. the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a sec- ond a1 a2 corruption. the error insertion is based on a rising edge detector. as such, the conrtol mustbe set to value 0 before trying to initiate a second 0 do not insert error. 1 insert error for number of frames in register hex 0c. 0 do not insert error. 1 insert error for 1 frame in b1 bits defined by register hex 0f.
50 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description per sts-12 alarm flag ais-p flag elastic store overflow flag enable/mask register [0:5] 26, 3e, 56, 6e, 86, 9e, b6, ce [0] 26, 3e, 56, 6e, 86, 9e, b6, ce [1] 26, 3e, 56, 6e, 86, 9e, b6,ce [2] 27, 3f, 57, 6f, 87, 9f, b7, cf [5:7] isreg isreg isreg iereg 0 0 0 0 these flag register bits per sts-12 alarm flag, ais-p flag, and elastic store overflow flag are the per-chan- nel interrupt status (consolidation) register.
agere systems inc. 51 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description fifo aligner threshold error flag receiver internal path par- ity error flag lof flag lvds link b1 parity error flag input parallel bus parity error flag toh serial input port par- ity error flag fifo oos error flag enable/mask register [0:5] 28, 40, 58, 70, 88, a0, b8, d0 [0] 28, 40, 58, 70, 88, a0, b8, d0 [1] 28, 40, 58, 70, 88, a0, b8, d0 [2] 28, 40, 58, 70, 88, a0, b8, d0 [3] 28, 40, 58, 70, 88, a0, b8, d0 [4] 28, 40, 58, 70, 88, a0, b8, d0 [5] 28, 40, 58, 70, 88, a0, b8, d0 [6] 29, 41, 59, 71, 89, a1, b9, d1 [0:5] iareg iareg iareg iareg iareg iareg iereg 0 0 0 0 0 0 00 these are the per sts-12 alarm flags. loss of frame. fifo out of sysc error flag.
52 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description ais interrupt flags 12, 9, 6, 3 ais interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2a, 42, 5a, 72, 8a, a2, ba, d2 [0:3] 2b, 43, 5b, 73, 8b, a3, bb, d3 [0:7] 2c, 44, 5c, 74, 8c, a4, bc, d4 [0:3] 2d, 45, 5d, 75, 8d, a5, bd, d5 [0:7] iareg iareg iereg iereg 0 00 0 00 these are the ais-p alarm flags. 1 if the serial input stream contains ais. es overflow flags 12, 9, 6, 3 es overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2e, 46, 5e, 76, 8e, a6, be, d6 [0:3] 2f, 47, 5f, 77, 8f, a7, bf, d7 [0:7] 30, 48, 60, 78, 90, a8, b0, d8 [0:3] 31, 49, 61, 79, 91, a9, b1, d9 [0:7] iareg iareg iereg iereg 0 00 0 00 these are the elastic store overflow alarm flags.
agere systems inc. 53 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description lvds link b1 parity error counter 32, 4a, 62, 7a, 92, aa, b2, da [0:7] counter 00 7 bit count + overflow ? reset on read. lof counter 33, 4b, 63, 7b, 93, ab, b3, db [0:7] counter 00 7 bit count + overflow ? reset on read increments on a change from in-frame to out-of-frame state. a1 a2 frame error counter 34, 4c, 64, 7c, 94, ac, b4, dc [0:7] counter 00 7 bit count + overflow ? reset on read. fifo depth register 35, 4d, 65, 7d, 95, ad, c5, dd [3:7] sreg 30 30 indicates fifo is half full. sampler phase error counter 36, 4e, 66, 7e, 96, ae, c6, de [0:7] counter 00 write 1 to clear. bypass register 37, 4f, 67,7f, 97, af, c7, df[0] creg 0 1: bypass pointer mover. bypass register 37, 4f, 67, 7f, 97, af, c7, df[1] creg 0 1: bypass alignment fifo + pointer mover. enable work/protect chan- nels 37, 4f, 67, 7f, 97, af, c7, df[2] creg 0 bit to control the lvds drivers/receivers to/from cdr. 0: use lvds drivers and receivers to/from pi-sched i/f block b (work channels). 1: use lvds drivers and receivers to/from pi-sched i/f block c (protect channels). sync control register 37, 4f, 67, 7f, 97, af, c7, df[3:4] creg 00 00: no alignment. 01: align with twin (i.e., stm b stream a). 10: align with all 4 (i.e., stm a all streams). 11: align with all 8 (i.e., stm a and b all streams). disable framer 37, 4f, 67, 7f, 97, af, c7, df[5] creg 0 0: enable framer. 1: disable sts-12 framing.
54 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc memory map (continued) table 12. memory map descriptions (continued) bit/register name(s) bit/ register location (hex) register type reset value (hex) description cdr control register 1 0xe0[6] creg 0 enables cdr test mode. initiates cdr ? s built-in self- test: 0: regular mode. 1: test mode. 0xe0[5] creg 0 enables bypassing of the 622 mhz clock synthesis with tstclk. 0: use pll. 1: bypass pll (uses tstclk as reference clock). 0xe0[4] creg 0 enables lvds loopback. 0: no loopback. 1: loopback. 0xe0[3] creg 0 when set to 1, controls bypass of 16 pll generated phases with 16 low-speed phases. cdr control register 1 0xe0[1] creg 0 en10bit. sets 10 to 1 mux/demux: 1 = 10:1 mux/demux. 0 = 8:1 mux/demux. 0xe0[0] creg 0 0 = long-haul i/f mode (enables cdr + stm opera- tion). 1 = short-haul i/f mode (disables cdr, enables pi- sched interfaces). cdr control register 4 0xe3[0:7] creg 0 enables 10-bit ethernet word alignment per channel. pi-sched i/f ctl register 0xf0[6] creg used during internal built-in self-test mode: 0 = no loopback. 1 = loopback. 0xf0[5] creg 0 reserved bit (read-only): 0 = shuts down bidi logic and ignores auxiliary bypass signals. always set to 0. 0xf0[0:4] creg indicates minimum cell size and will be used to detect cell underrun errors. pi-sched i/f status regis- ter 0xf1[0] sreg indicates completion of the internal test. only valid when otestenb (0xf2[7] is high): 0 = test running. 1 = test complete. 0xf1[1] sreg indicates success of the internal test. valid only when itestdone is high: 0 = test failed. 1 = test passed. pi-sched i/f ctl register 0xf2[0] creg 0 enables bypass of the pll circuit. tstclk is used in this mode. 0xf2[1] creg 0 1 = enables internal self-test of the shim block. both internal and external loopback paths exist during this test.
agere systems inc. 55 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 3+ fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 13. absolute maximum ratings * v dd a_shim and v dd a_stm are analog power supply inputs which need to be isolated from other power supplies on the board. recommended operating conditions table 14. recommended operating conditions * for recommended operating conditions for v dd io, see the series 4 fpga data sheet and the series 4 i/o buffer application note . ? v dd a_shim and v dd a_stm are analog power supply inputs which need to be isolated from other power supplies on the board. ? v dd 33 is an analog power supply for the fpga plls and needs to be isolated from other power supplies on the board. parameter symbol min max unit storage temperature t stg ? 65 150 c power supply voltage with respect to ground v dd 33 ? 0.3 4.2 v v dd io ? 0.3 4.2 v v dd 15 ? 0.3 2.0 v v dd a_shim* ? 0.3 2.0 v v dd a_stm* ? 0.3 2.0 v input signal with respect to ground ?? 0.3 v ddio + 0.3 v signal applied to high-impedance output ?? 0.3 v ddio + 0.3 v maximum package body temperature ?? 220 c parameter symbol min max unit power supply voltage with respect to ground* v dd 33 2.7 3.6 v v dd 15 1.4 1.6 v v dd a_shim ? 1.4 1.6 v v dd a_stm ? 1.4 1.6 v input voltages v in ? 0.3 v ddio + 0.3 v junction temperature t j ? 40 125 c
56 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc power supply decoupling lc circuit the 850 mhz hsi macro contains both analog and digital circuitry. the data recovery function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its 850 mhz reference frequency. the internal analog phase-locked loop contains a voltage-controlled oscillator. this circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. generated noise that contains frequency components beyond the band- width of the internal phase-locked loop (about 3 mhz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. thus, separate power supply pins are provided for these critical analog circuit ele- ments. additional power supply filtering in the form of a lc pi filter section will be used between the power supply source and these device pins as shown in figure 16. the corner frequency of the lc filter is chosen based on the power supply switching frequency, which is between 100 khz and 300 khz in most applications. capacitors c1 and c2 are large electrolytic capacitors to provide the basic cut-off frequency of the lc filter. for example, the cutoff frequency of the combination of these elements might fall between 5 khz and 50 khz. capaci- tor c3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. the physical location of capacitor c3 must be as close to the device lead as possible. multiple instances of capacitors c3 can be used if necessary. the recommended filter for the hsi macro is shown below: l = 4.7 h, rl = 1 ? , c1 = 0.01 f, c2 = 0.01 f, c 3 = 4 . 7 f. 5-9344(f) figure 16. sample power supply filter network for analog hsi power supply pins the rapid io interface to pi-sched also has internal plls that require an analog supply, v dd a_shim. the same power supply filter network shown above should be repeated and applied to the v dd a_shim inputs if this interface is used. if both the rapid io interface and the hsi interface are used, two seperate copies of this interface should be used. if the programmable plls on the fpga potrion of the device are to be used, then the v dd 33 supply must isolated in the same way. more information on this and other requirements for the fpga plls can be found in the series 4 pll application note. c2 + c3 + to device pll_v ssa c1 + from power supply source l v dda _stm
agere systems inc. 57 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc hsi electrical and timing characteristics table 15. absolute maximum ratings table 16. recommended operating conditions table 17. receiver specifications * scrambled data stream conforming to sonet sts-12 and sdh stm-4 data format using either a pn7 or pn9 sequence. ? pn7 characteristic is 1 + x 6 + x 7 . ? pn9 characteristic is 1 + x 4 + x 9 . alternatively 8b/10b encoded data is also valid input data. ? this sequence should not occur more than once per minute. ? translates to a frequency change of 500 ppm. a unit interval for 622.08 mbits/s data is 1.6075 ns. table 18. transmitter specifications table 19. synthesizer specifications * external 10 k ? resistor to analog ground required. ? translates to a frequency change of 500 ppm. parameter conditions min typ max unit power dissipation on v dd a_stm eight channels ?? 385 mw parameter conditions min typ max unit v dd 15 supply voltage ? 1.4 ? 1.6 v junction temperature t j ? 40 ? 125 c parameter conditions min typ max unit input data * stream of nontransitions ? ??? 60 bits phase change, input signal over a 200 ns time interval ? ?? 100 ps eye opening ? 0.4 ?? u i p-p jitter tolerance jitter tolerance: 250 khz 25 khz 2 khz ? ? ? ? ? ? ? 0.6 6 60 u i p-p u i p-p u i p-p parameter conditions min typ max unit output jitter, generated 250 khz to 5 mhz (measured with a spectrum analyzer) ?? 0.15 u i p-p output jitter, generated (including i/o buffers) 250 khz to 5 mhz ?? 0.25 u i p-p parameter conditions min typ max unit pll * loop bandwidth ??? 6mhz jitter peaking ??? 2db powerup reset time ? 10 ?? s lock aquisition time ??? 1ms input reference clock frequency ? 62.5 ? 212.50 mhz frequency deviation ??? 100 ppm phase change over a 200 ns time interval ? ?? 100 ps
58 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc parallel rapidio -like interface timing characteristics figure 17 illustrates the timing for the receive parallel interfaces a, b, and c (ddr). the recommended operating conditions for this interface are the same as for the hsi interface show in table 16. table 20 shows the worst case timing parameters for this interface made under these conditions. 5-9085.c(f) figure 17. receive parallel data/control timing table 20. parallel receive data/control timing figure 18 illustrates the timing for the transmit parallel interfaces a, b, and c (ddr). the recommended operating conditions for this interface are the same as for the hsi interface shown in table 16. table 21 shows the worst case timing parameters for this interface under these conditions. 2289(f) figure 18. transmit parallel data/control timing table 21. transmit parallel data/control timing symbol parameter ? 1 ? 2 ? 3 unit min max min max min max t1 clock frequency ? 266 ? 290 ? 315 mhz ? clock duty cycle 406040604060 % ? clock rise/fall time ? 1.0 ? 1.0 ? 1.0 v/ns t2 data/control setup time required 290 ? 270 ? 260 ? ps t3 data/control hold time required 290 ? 270 ? 260 ? ps symbol parameter ? 1 ? 2 ? 3 unit min max min max min max t4 clock frequency ? 266 ? 290 ? 315 mhz ? clock duty cycle 45 55 45 55 45 55 % ? clock rise/fall time ? 1.0 ? 1.0 ? 1.0 v/ns t5 data delay from clock edge 510 ? 510 ? 510 ? ps rxclk rxsoc p n p n t1 t3 t2 rxd[7:0] txclk txsoc p n p n t4 t5 txd[7:0] t5 t5 t5 t5 t5
agere systems inc. 59 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc embedded core lvds i/o table 22. driver dc data* *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. ? external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3%. table 23. driver ac data * *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. table 24. driver power consumption * *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. parameter symbol test conditions min typ max unit output voltage high, v oa or v ob v oh r load = 100 ? 1% ?? 1.475 ? v output voltage low, v oa or v ob v ol r load = 100 ? 1% 0.925 ? ?? v output differential voltage ? v od ? r load = 100 ? 1% 0.25 ? 0.45 ? v output offset voltage v os r load = 100 ? 1% 1.125* ? 1.275 ? v output impedance, differential r o v cm = 1.0 v and 1.4 v 80 100 120 ? r o mismatch between a and b ? r o v cm = 1.0 v and 1.4 v ?? 10 % change in differential voltage between complementary states ?? v od ? r load = 100 ? 1% ?? 25 mv change in output offset voltage between complementary states ? v os r load = 100 ? 1% ?? 25 mv output current i sa, i sb driver shorted to gnd ?? 24 ma output current i sab drivers shorted together ?? 12 ma power-off output leakage |ixa|, |ixb| v dd = 0 v v pad , v padn = 0 v ? 2.5 v ?? 10 ma parameter symbol test conditions min typ max unit v od fall time, 80% to 20% t f z l = 100 ? 1% c pad = 3.0 pf, c pad = 3.0 pf 100 ? 210 ps v od rise time, 20% to 80% t r z l = 100 ? 1% c pad = 3.0 pf, c pad = 3.0 pf 100 ? 210 ps differential skew |t phla ? t plhb | or |t phlb ? t plha | t skew1 any differential pair on package at 50% point of the transition ?? 50 ps channel-to-channel skew |tpdiffm ? tpdiffn|, t skew2 any two signals on package at 0 v differential ??? ps propagation delay time t plh t phl z l = 100 ? 1% c pad = 3.0 pf, c padn = 3.0 pf 0.54 0.55 0.77 0.76 1.10 1.09 ns ns parameter symbol test conditions min max unit driver dc power pd dc z l = 100 ? 1% ? 26.0 mw driver ac power pd ac z l = 100 ? 1% c pad = 3.0 pf, c padn = 3.0 pf ? 64 w/ mhz
60 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc embedded core lvds i/o (continued) lvds receiver buffer requirements table 25. receiver ac data * *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c , slow-fast process. table 26. receiver power consumption * *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c , slow-fast process. table 27. receiver dc data * *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c , slow-fast process. table 28. lvds operating parameters note:under worst-case operating condition, the lvds driver will withstand a disabled or unpowered receiver for an unlimited per iod of time with- out being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permanent d amage. the lvds driver supports hot insertion. under a well-controlled environment, the lvds i/o can drive backplane as well as cable. parameter symbol test conditions min max unit pulse-width distortion t pwd v idth = 100 mv, 450 mhz ? 160 ps propagation delay time t plh t phl c l = 0.5 pf 0.60 0.60 1.41 1.47 ns ns with common-mode variation (0 v to 2.4 v) ?? t pd ? c l = 0.5 pf ? 50 ps output rise time, 20% to 80% t r c l = 0.5 pf 150 350 ps output fall time, 80% to 20% t f c l = 0.5 pf 150 350 ps parameter symbol test conditions min max unit receiver dc power p rdc dc ? 20.4 mw receiver ac power p rac ac c l = 0.5 pf ? 4.5 w/ mhz parameter symbol test conditions min typ max unit input voltage range, via or vib v i ? v gpd ? < 925 mv dc ? 1 mhz 0.0 1.2 2.4 v input differential threshold v idth ? v gpd ? < 925 mv 450 mhz ? 100 ? 100 mv input differential hysteresis v hyst (+v idthh ) ? ( ? v idthl ) ??? mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 ? parameter test conditions min normal max unit transmit termination resistor ? 80 100 120 ? receiver termination resistor ? 80 100 120 ? temperature range ?? 40 ? 125 c power supply v dd 33 ? 3.1 ? 3.5 v power supply v dd 15 ? 1.4 ? 1.6 v power supply v ss ?? 0 ? v
agere systems inc. 61 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc input/output buffer measurement conditions (on-lvds buffer) note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . 5-3234(f) figure 19. ac test loads 5-3233.a(f) figure 20. output buffer delays 5-3235(f) figure 21. input buffer delays 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k ? b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pad out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pad in[i] in 3.0 v v ss v dd /2 v dd pad in in[i]
62 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc lvds buffer characteristics termination resistor the lvds drivers and receivers operate on a 100 ? differential impedance, as shown below. external resistors are not required. the differential driver and receiver buffers include termination resistors inside the device package, as shown in figure 22 below. 5-8703(f) figure 22. lvds driver and receiver and associated internal components lvds driver buffer capabilities under worst-case operating condition, the lvds driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when its outputs are short-circuited to each other or to ground, the lvds driver will not suffer permanent damage. figure 23 illustrates the terms associated with lvds driver and receiver pairs. 5-8704(f) figure 23. lvds driver and receiver 5-8705(f) figure 24. lvds driver lvds driver 50 ? 50 ? lvds receiver center tap device pins 100 ? external v gpd v oa v ob v ia v ib a b aa bb driver interconnect receiver v oa a v ob b c a c b r load v od = (v oa ? v ob ) v
agere systems inc. 63 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information this section describes the pins and signals that perform fpga-related functions. during configuration, the user- programmable i/os are 3-stated and pulled up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. table 29 . fpga common-function pin description symbol i/o description dedicated pins v dd 33 ? 3 v positive power supply. v dd 15 ? 1.5 v positive power supply for internal logic. v ddio ? positive power supply used by i/o banks. gnd ? ground supply. ptemp i temperature sensing diode pin. dedicated input. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i o in the master and asynchronous peripheral modes, cclk is an output which strobes con- figuration data in. in the slave or readback after configuration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that configura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of configuration and resets the bound- ary scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the i nit pin goes high. this pin always has an active pull-up. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configu- ration data out. if used in boundary scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral configuration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output. * the fpga states of operation section contains more information on how to control these signals during start up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options.
64 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 29. fpga common-function pin description (continued) symbol i/o description special-purpose pins (can also be used as a general i/o.) m[3:0] i during powerup and initialization, m0 ? m3 are used to select the configuration mode with their values latched on the rising edge of init . during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o.* pll_ck[0:7] i/o dedicated pcm clock pins. these pins are a user-programmable i/o pins if not used by plls. p[tbtr]clk[1:0][ tc] i/o pins dedicated for the primary clock. input pins on the middle of each side with differential pairing. they may be used as general i/o pins if not needed for clocking purposes. tdi, tck, tms i if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary scan functions are inhibited once configura- tion is complete. even if boundary scan is not used, either tck or tms must be held at logic 1 during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/busy /rclk o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* i/o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. hdc o high during configuration is output high until configuration is complete. it is used as a con- trol output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* ldc o low during configuration is output low until configuration is complete. it is used as a control output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low, open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, this pin is a user-programmable i/o pin.* cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during con- figuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
agere systems inc. 65 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 29. fpga common-function pin description (continued) symbol i/o description a[0:17] mpi_burst mpi_bdip mpi_tsz[1:0] i during mpi mode, the a[0:17] are used as the address bus driven by the powerpc bus master, utilizing the least significant bits of the powerpc 32-bit address. o during master parallel configuration mode, a[0:17] address the configuration eprom. in mpi mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during configuration, if not in master parallel or an mpi configuration mode, these pins are 3-stated with a pull-up enabled. it is driven low to indicate a burst transfer is in progress. driven high indicates that the current transfer is not a burst. it is driven by the powerpc processor assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. set 10 for byte, 01 for half-word, and 00 for word. if not used for mpi, these pins are user-programmable i/o pins.* mpi_ack oin powerpc mode mpi operation, this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used, this can be the amba bus clock. mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. mpi_rtry o this pin requests that the mpc860 relinquish the bus and retry the cycle. d[0:31] i/o selectable data bus width from 8-, 16-, 32-bit. driven by the bus master in a write transac- tion. driven by mpi in a read transaction. i d[0:7] receive configuration data during master parallel, peripheral, and slave parallel configuration modes and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:3] output internal status for asynchronous peripheral mode when rd is low. after configuration, the pins are user-programmable i/o pins.* dp[3:0] i/o selectable parity bus width from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:32]. after configuration, this pin is a user-programmable i/o pin.* din i during slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy- chained slave devices. data out on dout changes on the rising edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
66 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) this section describes device i/o signals to/from the embedded core excluding the signals at the cic boundary. table 30. fpsc function pin description *the v ss a_stm is combimed with v ss in packages that contain an internal v ss plane. symbol i/o description hsi lvds receive pins rxd_b_p0 i lvds work link ? channel aa (shared with rapidio port b) . rxd_b_n0 i lvds work link ? channel aa (shared with rapidio port b). rxd_c_p0 i lvds protect link ? channel aa (shared with rapidio port c). rxd_c_n0 i lvds protect link ? channel aa (shared with rapidio port c). rxd_b_p1 i lvds work link ? channel ab (shared with rapidio port b). rxd_b_n1 i lvds work link ? channel ab (shared with rapidio port b). rxd_c_p1 i lvds protect link ? channel ab (shared with rapidio port c). rxd_c_n1 i lvds protect link ? channel ab (shared with rapidio port c). rxd_b_p2 i lvds work link ? channel ac (shared with rapidio port b). rxd_b_n2 i lvds work link ? channel ac (shared with rapidio port b). rxd_c_p2 i lvds protect link ? channel ac (shared with rapidio port c). rxd_c_n2 i lvds protect link ? channel ac (shared with rapidio port c). rxd_b_p3 i lvds work link ? channel ad (shared with rapidio port b). rxd_b_n3 i lvds work link ? channel ad (shared with rapidio port b). rxd_c_p3 i lvds protect link ? channel ad (shared with rapidio port c). rxd_c_n3 i lvds protect link ? channel ad (shared with rapidio port c). rxd_b_p4 i lvds work link ? channel ba (shared with rapidio port b). rxd_b_n4 i lvds work link ? channel ba (shared with rapidio port b). rxd_c_p4 i lvds protect link ? channel ba (shared with rapidio port c). rxd_c_n4 i lvds protect link ? channel ba (shared with rapidio port c). rxd_b_p5 i lvds work link ? channel bb (shared with rapidio port b). rxd_b_n5 i lvds work link ? channel bb (shared with rapidio port b). rxd_c_p5 i lvds protect link ? channel bb (shared with rapidio port c). rxd_c_n5 i lvds protect link ? channel bb (shared with rapidio port c). rxd_b_p6 i lvds work link ? channel bc (shared with rapidio port b). rxd_b_n6 i lvds work link ? channel bc (shared with rapidio port b). rxd_c_p6 i lvds protect link ? channel bc (shared with rapidio port c). rxd_c_n6 i lvds protect link ? channel bc (shared with rapidio port c). rxd_b_p7 i lvds work link ? channel bd (shared with rapidio port b). rxd_b_n7 i lvds work link ? channel bd (shared with rapidio port b). rxd_c_p7 i lvds protect link ? channel bd (shared with rapidio port c). rxd_c_n7 i lvds protect link ? channel bd (shared with rapidio port c). dautrec i disable auto recovery for the pll. internal pull-down. v dda _stm i analog v dd 1.5 v power supply for the hsi block. v ssa _stm* i analog v ss for the hsi block.
agere systems inc. 67 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 30. fpsc function pin description (continued) symbol i/o description hsi lvds transmit pins txd_b_p0 i lvds work link ? channel aa (shared with rapidio port b). txd_b_n0 i lvds work link ? channel aa (shared with rapidio port b). txd_c_p0 i lvds protect link ? channel aa (shared with rapidio port c). txd_c_n0 i lvds protect link ? channel aa (shared with rapidio port c). txd_b_p1 i lvds work link ? channel ab (shared with rapidio port b). txd_b_n1 i lvds work link ? channel ab (shared with rapidio port b). txd_c_p1 i lvds protect link ? channel ab (shared with rapidio port c). txd_c_n1 i lvds protect link ? channel ab (shared with rapidio port c). txd_b_p2 i lvds work link ? channel ac (shared with rapidio port b). txd_b_n2 i lvds work link ? channel ac (shared with rapidio port b). txd_c_p2 i lvds protect link ? channel ac (shared with rapidio port c). txd_c_n2 i lvds protect link ? channel ac (shared with rapidio port c). txd_b_p3 i lvds work link ? channel ad (shared with rapidio port b). txd_b_n3 i lvds work link ? channel ad (shared with rapidio port b). txd_c_p3 i lvds protect link ? channel ad (shared with rapidio port c). txd_c_n3 i lvds protect link ? channel ad (shared with rapidio port c). txd_b_p4 i lvds work link ? channel ba (shared with rapidio port b). txd_b_n4 i lvds work link ? channel ba (shared with rapidio port b). txd_c_p4 i lvds protect link ? channel ba (shared with rapidio port c). txd_c_n4 i lvds protect link ? channel ba (shared with rapidio port c). txd_b_p5 i lvds work link ? channel bb (shared with rapidio port b). txd_b_n5 i lvds work link ? channel bb (shared with rapidio port b). txd_c_p5 i lvds protect link ? channel bb (shared with rapidio port c). txd_c_n5 i lvds protect link ? channel bb (shared with rapidio port c). txd_b_p6 i lvds work link ? channel bc (shared with rapidio port b). txd_b_n6 i lvds work link ? channel bc (shared with rapidio port b). txd_c_p6 i lvds protect link ? channel bc (shared with rapidio port c). txd_c_n6 i lvds protect link ? channel bc (shared with rapidio port c). txd_b_p7 i lvds work link ? channel bd (shared with rapidio port b). txd_b_n7 i lvds work link ? channel bd (shared with rapidio port b). txd_c_p7 i lvds protect link ? channel bd (shared with rapidio port c). txd_c_n7 i lvds protect link ? channel bd (shared with rapidio port c).
68 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 30. fpsc function pin description (continued) *the v ss a_shim is combimed with v ss in packages that contain an internal v ss plane. symbol i/o description hsi test signals tstclk i test clock for emulation of 622 mhz clock during pll bypass. internal pull-down. mreset i test mode reset. internal pull-down. testrst i resets receiver clock division counter. internal pull-up. resettx i resets transmitter clock division counter. internal pull-up. tstmux[9:0]s o test mode output port. scan_tstmd i test mode enable. must be tie-low for normal operation. scan_en i scan test enable. internal pull-up. tstsuftld i internal pull-down. e_toggle i internal pull-down. elsel i internal pull-down. exdnup i internal pull-down. rapidio lvds interface pins (receiver) rxd_a_p<7:0> i lvds data for rapidio , receiver port a. rxd_a_n<7:0> i lvds data for rapidio , receiver port a. rxsoc_a_p i lvds start-of-cell for rapidio , receiver port a. rxsoc_a_n i lvds start-of-cell for rapidio , receiver port a. rxclk_a_p i lvds receive clock for rapidio , receiver port a. rxclk_a_n i lvds receive clock for rapidio , receiver port a. lvctap_a<1:0> ? lvds input center tap (use 0.01 uf to gnd) internal pull-up. rxd_b_p<7:0> i lvds data for rapidio , receiver port b. rxd_b_n<7:0> i lvds data for rapidio , receiver port b. rxsoc_b_p i lvds start-of-cell for rapidio , receiver port b. rxsoc_b_n i lvds start-of-cell for rapidio , receiver port b. rxclk_b_p i lvds receive clock for rapidio , receiver port b. rxclk_b_n i lvds receive clock for rapidio , receiver port b. lvctap_b<4:0> ? lvds input center tap (use 0.01 f to gnd) internal pull-up. rxd_c_p<7:0> i lvds data for rapidio , receiver port c. rxd_c_n<7:0> i lvds data for rapidio , receiver port c. rxsoc_c_p i lvds start-of-cell for rapidio , receiver port c. rxsoc_c_n i lvds start-of-cell for rapidio , receiver port c. rxclk_c_p i lvds receive clock for rapidio , receiver port c. rxclk_c_n i lvds receive clock for rapidio , receiver port c. lvctap_c<4:0> ? lvds input center tap (use 0.01 f to gnd) internal pull-up. ref10 ? lvds reference voltage: 1.0 v 3%. ref14 ? lvds reference voltage: 1.4 v 3%. reshi ? lvds resistor high pin ( 100 ? in series with reslo). reslo ? lvds resistor low pin ( 100 ? in series with reshi). v dd a_shim i analog v dd 1.5 v power supply for the rapid io block. v ss a_shim i analog v ss for the rapid io block.
agere systems inc. 69 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 30. fpsc function pin description (continued) symbol i/o description rapidio lvds interface pins (transmitter) txd_a_p<7:0> o lvds data for rapidio , transmitter port a. txd_a_n<7:0> o lvds data for rapidio , transmitter port a. txsoc_a_p o lvds start-of-cell for rapidio , transmitter port a. txsoc_a_n o lvds start-of-cell for rapidio , transmitter port a. txclk_a_p o lvds receive clock for rapidio , transmitter port a. txclk_a_n o lvds receive clock for rapidio , transmitter port a. txd_b_p<7:0> o lvds data for rapidio , transmitter port b. txd_b_n<7:0> o lvds data for rapidio , transmitter port b. txsoc_b_p o lvds start-of-cell for rapidio , transmitter port b. txsoc_b_n o lvds start-of-cell for rapidio , transmitter port b. txclk_b_p o lvds receive clock for rapidio , transmitter port b. txclk_b_n o lvds receive clock for rapidio , transmitter port b. txd_c_p<7:0> o lvds data for rapidio , transmitter port c. txd_c_n<7:0> o lvds data for rapidio , transmitter port c. txsoc_c_p o lvds start-of-cell for rapidio , transmitter port c. txsoc_c_n o lvds start-of-cell for rapidio , transmitter port c. txclk_c_p o lvds receive clock for rapidio , transmitter port c. txclk_c_n o lvds receive clock for rapidio , transmitter port c. misc system signals rst_n i reset the core only. the fpga logic is not reset by rst_n. internal pull down allows chip to stay in reset state when external driver loses power. sys_clk_p i lvds system clock, 50% duty cycle, also the reference clock of pll. sys_clk_n i lvds system clock, 50% duty cycle, also the reference clock of pll. gclk_p i lvds clock for rapidio pll internal pull-up. gclk_n i lvds clock for rapidio pll internal pull-up. dxp ? temperature-sensing diode (anode +). dxn ? temperature-sensing diode (cathode ? ). lvctap_sk o lvds center-tap for sys_clk (use 0.01 f to gnd). lvctap_gk o lvds center-tap for gclk (use 0.01 f to gnd).
70 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) in table 31, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core. table 31. embedded core/fpga interface signal description pin name i/o description stm or 8b/10b signals dinaa<7:0> i parallel bus of stm slice a, transmitter a. msb is bit 7. dinaa_par i parity for stm slice a, transmitter a. dinaa_fp i frame pulse or k control for stm slice a, transmitter a. dinab<7:0> i parallel bus of stm slice a, transmitter b. msb is bit 7. dinab_par i parity for stm slice a, transmitter b. dinab_fp i frame pulse or k control for stm slice a, transmitter b. dinac<7:0> i parallel bus of stm slice a, transmitter c. msb is bit 7. dinac_par i parity for stm slice a, transmitter c. dinac_fp i frame pulse or k control for stm slice a, transmitter c. dinad<7:0> i parallel bus of stm slice a, transmitter d. msb is bit 7. dinad_par i parity for stm slice a, transmitter d. dinad_fp i frame pulse or k control for stm slice a, transmitter d. dinba<7:0> i parallel bus of stm slice b, transmitter a. msb is bit 7. dinba_par i parity for stm slice b, transmitter a. dinba_fp i frame pulse or k control for stm slice b, transmitter a. dinbb<7:0> i parallel bus of stm slice b, transmitter b. msb is bit 7. dinbb_par i parity for stm slice b, transmitter b. dinbb_fp i frame pulse or k control for stm slice b, transmitter b. dinbc<7:0> i parallel bus of stm slice b, transmitter c. msb is bit 7. dinbc_par i parity for stm slice b, transmitter c. dinbc_fp i frame pulse or k control for stm slice b, transmitter c. dinbd<7:0> i parallel bus of stm slice b, transmitter d. msb is bit 7. dinbd_par i parity for stm slice b, transmitter d. dinbd_fp i frame pulse or k control for stm slice b, transmitter d. doutaa<7:0> o parallel bus of stm slice a, receiver a. msb is bit 7. doutaa_par o parity for parallel bus of stm slice a, receiver a. doutaa_spe o spe signal for parallel bus of stm slice a, receiver a. doutaa_c1j1 o c1j1 signal for parallel bus of stm slice a, receiver a. doutaa_en o enable for parallel bus of stm slice a, receiver a. doutaa_fp o frame pulse or commadet for parallel bus of stm slice a, receiver a. doutab<7:0> o parallel bus of stm slice a, receiver b. msb is bit 7. doutab_par o parity for parallel bus of stm slice a, receiver b. doutab_spe o spe signal for parallel bus of stm slice a, receiver b. doutab_c1j1 o c1j1 signal for parallel bus of stm slice a, receiver b. doutab_en o enable for parallel bus of stm slice a, receiver b. doutab_fp o frame pulse or commadet for parallel bus of stm slice a, receiver b.
agere systems inc. 71 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description stm or 8b/10b signals (continued) doutac<7:0> o parallel bus of stm slice a, receiver c. msb is bit 7. doutac_par o parity for parallel bus of stm slice a, receiver c. doutac_spe o spe signal for parallel bus of stm slice a, receiver c. doutac_c1j1 o c1j1 signal for parallel bus of stm slice a, receiver c. doutac_en o enable for parallel bus of stm slice a, receiver c. doutac_fp o frame pulse or commadet for parallel bus of stm slice a, receiver c. doutad<7:0> o parallel bus of stm slice a, receiver d. msb is bit 7. doutad_par o parity for parallel bus of stm slice a, receiver d. doutad_spe o spe signal for parallel bus of stm slice a, receiver d. doutad_c1j1 o c1j1 signal for parallel bus of stm slice a, receiver d. doutad_en o enable for parallel bus of stm slice a, receiver d. doutad_fp o frame pulse or commadet for parallel bus of stm slice a, receiver d. doutba<7:0> o parallel bus of stm slice b, receiver a. msb is bit 7. doutba_par o parity for parallel bus of stm slice b, receiver a. doutba_spe o spe signal for parallel bus of stm slice b, receiver a. doutba_c1j1 o c1j1 signal for parallel bus of stm slice b, receiver a. doutba_en o enable for parallel bus of stm slice b, receiver a. doutba_fp o frame pulse or commadet for parallel bus of stm slice b, receiver a. doutbb<7:0> o parallel bus of stm slice b, receiver b. msb is bit 7. doutbb_par o parity for parallel bus of stm slice b, receiver b. doutbb_spe o spe signal for parallel bus of stm slice b, receiver b. doutbb_c1j1 o c1j1 signal for parallel bus of stm slice b, receiver b. doutbb_en o enable for parallel bus of stm slice b, receiver b. doutbb_fp o frame pulse or commadet for parallel bus of stm slice b, receiver b. doutbc<7:0> o parallel bus of stm slice b, receiver c. msb is bit 7. doutbc_par o parity for parallel bus of stm slice b, receiver c. doutbc_spe o spe signal for parallel bus of stm slice b, receiver c. doutbc_c1j1 o c1j1 signal for parallel bus of stm slice b, receiver c. doutbc_en o enable for parallel bus of stm slice b, receiver c. doutbc_fp o frame pulse or commadet for parallel bus of stm slice b, receiver c. doutbd<7:0> o parallel bus of stm slice b, receiver d. msb is bit 7. doutbd_par o parity for parallel bus of stm slice b, receiver d. doutbd_spe o spe signal for parallel bus of stm slice b, receiver d. doutbd_c1j1 o c1j1 signal for parallel bus of stm slice b, receiver d. doutbd_en o enable for parallel bus of stm slice b, receiver d. doutbd_fp o frame pulse or commadet for parallel bus of stm slice b, receiver d.
72 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description toh signals toh_clk i tx and rx toh serial links clock (25 mhz to 77.76 mhz). toh_inaa i toh serial link for stm slice a, transmitter a. toh_inab i toh serial link for stm slice a, transmitter b. toh_inac i toh serial link for stm slice a, transmitter c. toh_inad i toh serial link for stm slice a, transmitter d. toh_inba i toh serial link for stm slice b, transmitter a. toh_inbb i toh serial link for stm slice b, transmitter b. toh_inbc i toh serial link for stm slice b, transmitter c. toh_inbd i toh serial link for stm slice b, transmitter d. tx_toh_ck_en i tx toh serial link clock enable. toh_outaa o toh serial link for stm slice a, receiver a. toh_outab o toh serial link for stm slice a, receiver b. toh_outac o toh serial link for stm slice a, receiver c. toh_outad o toh serial link for stm slice a, receiver d. toh_outba o toh serial link for stm slice b, receiver a. toh_outbb o toh serial link for stm slice b, receiver b. toh_outbc o toh serial link for stm slice b, receiver c. toh_outbd o toh serial link for stm slice b, receiver d. rx_toh_ck_en o rx toh serial link clock enable. rx_toh_fp o rx toh serial link frame pulse. toh_ck_fp_en o a soft register bit available to enable rx toh clock and frame pulse. toh_aa_en o rx toh enable, soft register. and output of resistor channel aa enable and hi-z control of toh data output aa. toh_ab_en o rx toh enable, soft register. and output of resistor channel ab enable and hi-z control of toh data output ab. toh_ac_en o rx toh enable, soft register. and output of resistor channel ac enable and hi-z control of toh data output ac. toh_ad_en o rx toh enable, soft register. and output of resistor channel ad enable and hi-z control of toh data output ad. toh_ba_en o rx toh enable, soft register. and output of resistor channel ba enable and hi-z control of toh data output ba. toh_bb_en o rx toh enable, soft register. and output of resistor channel bb enable and hi-z control of toh data output bb. toh_bc_en o rx toh enable, soft register. and output of resistor channel bc enable and hi-z control of toh data output bc. toh_bd_en o rx toh enable, soft register. and output of resistor channel bd enable and hi-z control of toh data output bd.
agere systems inc. 73 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description stm clock and control sys_fp i system frame pulse for transmitter section. line_fp i line frame pulse for receiver section. fpga_sysclk o system clock (sys_clk). this signal is routed onto a primary clock net inside the fpga, with very low skew. prot_switch_aa i stm channel protection enable for channels aa and ab. active-high. prot_switch_ac i stm channel protection enable for channels ac and ac. active-high. prot_switch_ba i stm channel protection enable for channels ba and bb. active-high. prot_switch_bc i stm channel protection enable for channels bc and bd. active-high. lvds_prot_aa i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_ab i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_ac i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_ad i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_ba i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_bb i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_bc i lvds buffer redundancy select for rx channel aa. active-high for redundant link. lvds_prot_bd i lvds buffer redundancy select for rx channel aa. active-high for redundant link. core_ready o during powerup and fpga configuration sequence, the core_ready is held low. at the end of fpga configuration, the core_ready will be held low for six clock (sys_clk) cycles and then go active-high. flag indicates that the embedded core is out of its reset state. cdr_clk_aa o recovered clock for stm slice a, channel a. cdr_clk_ab o recovered clock for stm slice a, channel b. cdr_clk_ac o recovered clock for stm slice a, channel c. cdr_clk_ad o recovered clock for stm slice a, channel d. cdr_clk_ba o recovered clock for stm slice b, channel a. cdr_clk_bb o recovered clock for stm slice b, channel b. cdr_clk_bc o recovered clock for stm slice b, channel c. cdr_clk_bd o recovered clock for stm slice b, channel d. 8b/10b mode signals tx_k_ctrl_aa i k control bit for channel aa. tx_k_ctrl_ab i k control bit for channel ab. tx_k_ctrl_ac i k control bit for channel ac. tx_k_ctrl_ad i k control bit for channel ad. tx_k_ctrl_ba i k control bit for channel ba. tx_k_ctrl_bb i k control bit for channel bb. tx_k_ctrl_bc i k control bit for channel bc. tx_k_ctrl_bd i k control bit for channel bd.
74 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description rapidio signals (channel a) csysenb_a o system cell processing enable. after reset is released, drive this signal high when rapidio is ready to transmit cells. this signal should be active after all control signals into the rapidio are stable. rstn_rx_a o synchronous reset for all memory elements clocked by wrxclk_a_fpga (derived from pll). utxd_a<31:0> o transmit data bus containing four octets synchronized with the rising edge of the 60 mhz ? 146 mhz wutxclk_fpga (derived from pll) is clocked into the transmit fifo within the rapidio . utxsoc_a o start of cell originating with the core and synchronized with the rising edge of wutxclk_fpga into the transmit fifo. indi- cates that the first data word on txd_a bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_a o synchronous reset for all memory elements in the wutxclk_fpga domain. utxtristn_a o output 3-state enable (active-low). when active, the txd_a, txsoc_a, and txclk_a lvds drivers are 3-stated. ytristn_a o 3-state override for transmit outputs (active-low). this signal is ignored during reset, but takes priority over all 3-state control signals otherwise. zrxd_a<31:0> o 32-bit data from the receive module. the bus contains four octets and reflects data received via the high-speed rxd_a data bus. zrxsoc_a o indicates the presence of the first octet of a new cell within the first 32-bit data word on the rxd_a bus in bit positions <31:24>. zrxsocviol_a o indicates a minimum cell violation within the receive module. this signal will transition active-high coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_a o indicates an alignment error. an active state signals rxsoc was captured on a negative rxclk edge. this signal will stay high for a single wrxclk_a_fpga cycle coincident with rxsoc. zclkstat_a o indicates the loss or absence of a clock on the lvds clock (rxclk). after the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. wrxclk_a_fpga o derived from high-speed lvds clock rxclk (= rxclk/2). rapidio signals (channel b) csysenb_b i system cell processing enable. after reset is released, drive this signal high when rapidio is ready to transmit cells. this signal should be active after all control signals into the rapidio are stable.
agere systems inc. 75 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description rapidio signals (channel b) (continued) rstn_rx_b i synchronous reset for all memory elements clocked by wrxclk_b_fpga (derived from pll). utxd_b<31:0> i transmit data bus containing four octets synchronized with the rising edge of the 60 mhz ? 146 mhz wutxclk_fpga (derived from pll) is clocked into the transmit fifo within the rapidio . utxsoc_b i start of cell originating with the core and synchronized with the rising edge of wutxclk_fpga into the transmit fifo. indi- cates that the first data word on txd_b bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_b i synchronous reset for all memory elements in the wutxclk_fpga domain. utxtristn_b i output 3-state enable (active-low). when active, the txd_b, txsoc_b, and txclk_b lvds drivers are 3-stated. ytristn_b i 3-state override for transmit outputs (active-low). this signal is ignored during reset, but takes priority over all 3-state control signals otherwise. zrxd_b<31:0> o 32-bit data from the receive module. the bus contains four octets and reflects data received via the high-speed rxd_b data bus. zrxsoc_b o indicates the presence of the first octet of a new cell within the first 32-bit data word on the rxd_b bus in bit positions <31:24>. zrxsocviol_b o indicates a minimum cell violation within the receive module. this signal will transition active-high coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_b o indicates an alignment error. an active state signals rxsoc was captured on a negative rxclk edge. this signal will stay high for a single wrxclk_b_fpga cycle coincident with rxsoc. zclkstat_b o indicates the loss or absence of a clock on the lvds clock (rxclk). after the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. wrxclk_b_fpga o derived from high-speed lvds clock rxclk (= rxclk/2). rapidio signals (channel c) csysenb_c i system cell processing enable. after reset is released, drive this signal high when rapidio is ready to transmit cells. this signal should be active after all control signals into the rapidio are stable. rstn_rx_c i synchronous reset for all memory elements clocked by wrxclk_c_fpga (derived from pll).
76 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 31. embedded core/fpga interface signal description (continued) pin name i/o description rapidio signals (channel c) (continued) utxd_c<31:0> i transmit data bus containing four octets synchronized with the rising edge of the 60 mhz ? 146 mhz wutxclk_fpga (derived from pll) is clocked into the transmit fifo within the rapidio . utxsoc_c i start of cell originating with the core and synchronized with the rising edge of wutxclk_fpga into the transmit fifo. indi- cates that the first data word on txd_c bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_c i synchronous reset for all memory elements in the wutxclk_fpga domain. utxtristn_c i output 3-state enable (active-low). when active, the txd_c, txsoc_c, and txclk_c lvds drivers are 3-stated. ytristn_c i 3-state override for transmit outputs (active-low). this signal is ignored during reset, but takes priority over all 3-state control signals otherwise. zrxd_c<31:0> o 32-bit data from the receive module. the bus contains four octets and reflects data received via the high-speed rxd_c data bus. zrxsoc_c o indicates the presence of the first octet of a new cell within the first 32-bit data word on the rxd_c bus in bit positions <31:24>. zrxsocviol_c o indicates a minimum cell violation within the receive module. this signal will transition active-high coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_c o indicates an alignment error. an active state signals rxsoc was captured on a negative rxclk edge. this signal will stay high for a single wrxclk_c_fpga cycle coincident with rxsoc. zclkstat_c o indicates the loss or absence of a clock on the lvds clock (rxclk). after the validation of the absence of the clock, this signal will stay high for the duration of the absence of the clock. wrxclk_c_fpga o derived from high-speed lvds clock rxclk (= rxclk/2). rapidio signals wutxclk_fpga o one x core clock (60 mhz ? 146 mhz) generated from an internal pll circuit. input data on utxd<31:0> and utxsco are synchronous to this clock. the transmit fifo inputs are clocked by this clock. the test interface module also runs off this clock. this clock is sent to the fpga logic. halfclk_fpga o 1/2 x main pll output clock. phase aligned with pfclk. nominal frequency range is 30 mhz to 73 mhz. duty cycle spec is 47%/53%.
agere systems inc. 77 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) package pinouts table 33 and table 34 provide the package pin and pin function for the ort8850 fpsc and packages. the bond pad name is identified in the pio nomeclature used in the orca foundry design editor. the bank column provides information as to which output voltage level bank the given pin is in. the group column pro- vides information as to the group of pins the given pin is in. this is used to show which vref pin is used to provide the reference voltage for single-ended limited- swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the vref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no con- nects). when a package pin is to be left as a no con- nect for a specific die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads. the pinouts for both the ort8850h and ort8850l in the 680 pbgam package are shown in table 32. in order to allow pin-for-pin compatible board layouts that can accommodate both devices, some key compatibil- ity issues include the following.: unused pins. as shown in table 32, there are 19 balls that are not available in the ort8850l, but are available in the ort8850h. these user i/os should not be used if the ort8850l may be used. shared control signals on i/o registers. the orca series 4 architecture shares clock and control signals between two adjacent i/o pads. if i/o regis- ters are used, incompatibilities may arise between ort8850l and ort8850h when different clock or control signals are needed on adjacent package pins. this is because one device may allow indepen- dent clock or control signals on these adjacent pins, while the other may force them to be the same. there are two ways to avoid this issue. ? always keep an open bonded pin (non-bonded pins for the ort8850l do not count) between pins that require different clock or control signals. note that this open pin can be used to connect signals that do not require the use of i/o registers to meet timing. ? place and route the design in both the ort8850h and ort8850l to verify both produce valid designs. note that this method guarantees the current design, but does not necessarily guard against issues that can occur when design changes are made that affect i/o registers. ? 2x/4x i/o shift registers. if 2x i/o shift registers or 4x i/o shift registers are used in the design, this may cause incompatibilities between the ort880l and ort8850h because only the a and c i/os in a pic support 2x i/o shift registers and only a i/os supports 4x i/o shift register mode. a and c i/os are shown in the following pinout tables under the i/o pad columns as those ending in a or c. edge clock input pins. the input buffers for fast edge clocks are only available at the c i/o pad. the c i/os are shown in the following pinout tables under the i/o pad colums as those ending in c. unused pins. one of the incompatibilities is due to the fact that the ort8850l is a much smaller array and does not provide as many programmable ios (pios). table 32 shows a list of bonded ort8850h pios that are unused in the ort8850l. table 32. ort8850h pins that are unused in ort8850l users should avoid using these pins if they plan to migrate their ort8850h design to an ort8850l. bga ball bonds ort8850h pios k4 pl11a m5 pl13a r5 pl20a t5 pl21a w4 pl27a aa2 pl28a y4 pl29a ac4 pl35a ad5 pl37a ag1 pl38a ap4 pb3a ak10 pb9a ak11 pb10a am9 pb11a an9 pb12a am14 pb19a an14 pb20a d11 pt12a e13 pt11a
78 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout ba352 v dd io bank vref group i/o ort8850l additional function pair a1 ?? v ss v ss ?? b1 ?? v dd 33 v dd 33 ?? c2 ?? o prd_data rd_data/tdo ? aa23 ?? v dd 15 v dd 15 ?? c1 ?? i preset_n reset_n ? e4 ?? i prd_cfg_n rd_cfg_n ? d1 ?? i pprgrm_n prgrm_n ? d2 0 (tl) ? v dd io0 v dd io0 ?? e3 0 (tl) 7 io pl2d pll_ck0c/hppll l12c_a0 e2 0 (tl) 7 io pl2c pll_ck0t/hppll l12t_a0 a2 ?? v ss v ss ?? e1 0 (tl) 7 io pl2a vref_0_07 ? f3 0 (tl) 7 io pl3d d5 l13c_a0 f2 0 (tl) 7 io pl3c d6 l13t_a0 g4 0 (tl) 8 io pl4d hdc l14c_a0 g3 0 (tl) 8 io pl4c ldc_n l14t_a0 a26 ?? v ss v ss ?? g2 0 (tl) 9 io pl5c d7 ? f1 0 (tl) ? v dd io0 v dd io0 ?? h2 0 (tl) 9 io pl5b vref_0_09 l15c_a0 h3 0 (tl) 9 io pl5a a17/ppc_a31 l15t_a0 g1 0 (tl) 9 io pl6d cs0_n l16c_a0 h1 0 (tl) 9 io pl6c cs1 l16t_a0 ac13 ?? v ss v ss ?? j4 0 (tl) 10 io pl7d init_n l17c_a0 j3 0 (tl) 10 io pl7c dout l17t_a0 aa4 ?? v dd 15 v dd 15 ?? j2 0 (tl) 10 io pl7b vref_0_10 l18c_a0 j1 0 (tl) 10 io pl7a a16/ppc_a30 l18t_a0 k4 7 (cl) 1 io pl8d a15/ppc_a29 l1c_a0 k3 7 (cl) 1 io pl8c a14/ppc_a28 l1t_a0 k2 7 (cl) 1 io pl9d vref_7_01 l2c_a0 k1 7 (cl) 1 io pl9c d4 l2t_a0 ad3 ?? v ss v ss ?? l1 7 (cl) 2 io pl10d rdy/busy_n/rclk l3c_a0 l2 7 (cl) 2 io pl10c vref_7_02 l3t_a0 l3 7 (cl) ? v dd io7 v dd io7 ?? m1 7 (cl) 2 io pl10b a13/ppc_a27 l4c_a0 m2 7 (cl) 2 io pl10a a12/ppc_a26 l4t_a0 ae1 ?? v ss v ss ?? m4 7 (cl) 3 io pl11b a11/ppc_a25 l5c_a0 m3 7 (cl) 3 io pl11a vref_7_03 l5t_a0
agere systems inc. 79 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair ac11 ?? v dd 15 v dd 15 ?? n2 7 (cl) 4 io pl13d rd_n/mpi_strb_n l6c_a0 n3 7 (cl) 4 io pl13c vref_7_04 l6t_a0 ae2 ?? v ss v ss ?? n1 7 (cl) 4 io pl14d plck0c l7c_a0 p1 7 (cl) 4 io pl14c plck0t l7t_a0 p2 7 (cl) ? v dd io7 v dd io7 ?? ae25 ?? v ss v ss ?? p3 7 (cl) 5 io pl15d a10/ppc_a24 l8c_a0 p4 7 (cl) 5 io pl15c a9/ppc_a23 l8t_a0 af1 ?? v ss v ss ?? r1 7 (cl) 5 io pl16d a8/ppc_a22 l9c_a0 r2 7 (cl) 5 io pl16c vref_7_05 l9t_a0 ac16 ?? v dd 15 v dd 15 ?? r3 7 (cl) 6 io pl17d plck1c l10c_a0 r4 7 (cl) 6 io pl17c plck1t l10t_a0 af25 ?? v ss v ss ?? t1 7 (cl) 6 io pl17b vref_7_06 l11c_a0 t2 7 (cl) 6 io pl17a a7/ppc_a21 l11t_a0 u1 7 (cl) 6 io pl18d a6/ppc_a20 l12c_a0 u2 7 (cl) 6 io pl18c a5/ppc_a19 l12t_a0 t3 7 (cl) ? v dd io7 v dd io7 ?? v1 7 (cl) 7 io pl19d wr_n/mpi_rw l13c_a0 v2 7 (cl) 7 io pl19c vref_7_07 l13t_a0 w1 7 (cl) 8 io pl20d a4/ppc_a18 l14c_a0 y1 7 (cl) 8 io pl20c vref_7_08 l14t_a0 u3 7 (cl) 8 io pl20b a3/ppc_a17 l15c_a0 u4 7 (cl) 8 io pl20a a2/ppc_a16 l15t_a0 v3 7 (cl) 8 io pl21d a1/ppc_a15 l16c_d0 w2 7 (cl) 8 io pl21c a0/ppc_a14 l16t_d0 y2 7 (cl) 8 io pl21b dp0 l17c_d0 w3 7 (cl) 8 io pl21a dp1 l17t_d0 aa1 6 (bl) 1 io pl22d d8 l1c_a0 ab1 6 (bl) 1 io pl22c vref_6_01 l1t_a0 b25 ?? v ss v ss ?? w4 6 (bl) 1 io pl22b d9 l2c_d0 y3 6 (bl) 1 io pl22a d10 l2t_d0 y4 6 (bl) ? v dd io6 v dd io6 ?? aa2 6 (bl) 3 io pl24d d11 l3c_a0 aa3 6 (bl) 3 io pl24c d12 l3t_a0 b26 ?? v ss v ss ?? ab3 6 (bl) 3 io pl25d vref_6_03 l4c_a0
80 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair ab2 6 (bl) 3 io pl25c d13 l4t_a0 ac2 6 (bl) 4 io pl26c vref_6_04 ? c24 ?? v ss v ss ?? ac1 6 (bl) 4 io pl27d pll_ck7c/hppll l5c_a0 ad1 6 (bl) 4 io pl27c pll_ck7t/hppll l5t_a0 c3 ?? v ss v ss ?? d14 ?? v ss v ss ?? ab4 ?? iptemp ptemp ? ac3 6 (bl) ? v dd io6 v dd io6 ?? ac21 ?? v dd 15 v dd 15 ?? ad2 ?? io lvds_r lvds_r ? af2 ?? v dd 33 v dd 33 ?? d19 ?? v ss v ss ?? ae3 ?? v dd 33 v dd 33 ?? ac6 ?? v dd 15 v dd 15 ?? af3 6 (bl) 5 io pb2a dp2 ? ad4 6 (bl) 5 io pb2c pll_ck6t/ppll l6t_a0 ae4 6 (bl) 5 io pb2d pll_ck6c/ppll l6c_a0 ac5 6 (bl) 5 io pb3c vref_6_05 l7t_a0 ad5 6 (bl) 5 io pb3d dp3 l7c_a0 d23 ?? v ss v ss ?? ae5 6 (bl) 6 io pb4c vref_6_06 l8t_d0 af4 6 (bl) 6 io pb4d d14 l8c_d0 ac7 6 (bl) ? v dd io6 v dd io6 ?? ad6 6 (bl) 7 io pb5c d15 l9t_a0 ae6 6 (bl) 7 io pb5d d16 l9c_a0 af5 6 (bl) 7 io pb6a d17 l10t_a0 af6 6 (bl) 7 io pb6b d18 l10c_a0 d4 ?? v ss v ss ?? ad7 6 (bl) 7 io pb6c vref_6_07 l11t_a0 ae7 6 (bl) 7 io pb6d d19 l11c_a0 ad8 6 (bl) 8 io pb7a d20 l12t_a0 ae8 6 (bl) 8 io pb7b d21 l12c_a0 af7 6 (bl) 8 io pb7c vref_6_08 l13t_a0 af8 6 (bl) 8 io pb7d d22 l13c_a0 d9 ?? v ss v ss ?? ac9 6 (bl) 9 io pb8c d23 l14t_a0 ad9 6 (bl) 9 io pb8d d24 l14c_a0 ae9 6 (bl) 9 io pb9c vref_6_09 l15t_a0 af9 6 (bl) 9 io pb9d d25 l15c_a0 ac10 6 (bl) 10 io pb10c d26 l16t_a0 ad10 6 (bl) 10 io pb10d d27 l16c_a0
agere systems inc. 81 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair ae10 6 (bl) ? v dd io6 v dd io6 ?? ad11 6 (bl) 10 io pb11c vref_6_10 l17t_a0 ae11 6 (bl) 10 io pb11d d28 l17c_a0 af10 6 (bl) 11 io pb12a d29 l18t_a0 af11 6 (bl) 11 io pb12b d30 l18c_a0 ac12 6 (bl) 11 io pb12c vref_6_11 l19t_a0 ad12 6 (bl) 11 io pb12d d31 l19c_a0 ae12 5 (bc) 1 io pb14a ? l1t_a0 af12 5 (bc) 1 io pb14b ? l1c_a0 h4 ?? v ss v ss ?? ae13 5 (bc) 1 io pb15a vref_5_01 l2t_a0 af13 5 (bc) 1 io pb15b ? l2c_a0 ad13 5 (bc) ? v dd io5 v dd io5 ?? af14 5 (bc) 2 io pb16a pbck0t l3t_a0 ae14 5 (bc) 2 io pb16b pbck0c l3c_a0 d11 ?? v dd 15 v dd 15 ?? ad14 5 (bc) 2 io pb17a vref_5_02 l4t_a0 ac14 5 (bc) 2 io pb17b ? l4c_a0 j23 ?? v ss v ss ?? af15 5 (bc) 3 io pb18a ? l5t_a0 ae15 5 (bc) 3 io pb18b vref_5_03 l5c_a0 n4 ?? v ss v ss ?? ad15 5 (bc) 3 io pb19a ? l6t_a0 ac15 5 (bc) 3 io pb19b ? l6c_a0 p23 ?? v ss v ss ?? af16 5 (bc) 3 io pb20a pbck1t l7t_a0 af17 5 (bc) 3 io pb20b pbck1c l7c_a0 ae16 5 (bc) 4 io pb21a ? l8t_a0 ad16 5 (bc) 4 io pb21b ? l8c_a0 v4 ?? v ss v ss ?? ae17 5 (bc) 4 io pb22a ? l9t_a0 ad17 5 (bc) 4 io pb22b vref_5_04 l9c_a0 w23 ?? v ss v ss ?? ac17 5 (bc) ? v dd io5 v dd io5 ?? af18 5 (bc) 5 io pb23c ? l10t_a0 af19 5 (bc) 5 io pb23d vref_5_05 l10c_a0 l11 ?? v ss v ss ?? ae18 5 (bc) 6 io pb26a ? l11t_a0 ad18 5 (bc) 6 io pb26b vref_5_06 l11c_a0 d16 ?? v dd 15 v dd 15 ?? l12 ?? v ss v ss ?? l13 ?? v ss v ss ??
82 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair ae19 ?? o txd_c0_n ? l1n_a0 ad19 ?? o txd_c0_p ? l1p_a0 ac19 ?? v dd 33 v dd 33 ?? af20 ?? o txd_c1_n ? l2n_a0 af21 ?? o txd_c1_p ? l2p_a0 l14 ?? v ss v ss ?? ae20 ?? o txd_c2_n ? l3n_a0 ad20 ?? o txd_c2_p ? l3p_a0 ac20 ?? v dd 33 v dd 33 ?? ae21 ?? o txd_c3_n ? l4n_a0 ad21 ?? o txd_c3_p ? l4p_a0 l15 ?? v ss v ss ?? d21 ?? v dd 15 v dd 15 ?? af22 ?? o txsoc_c_n ? l5n_a0 af23 ?? otxsoc_c_p ? l5p_a0 ae22 ?? v dd 33 v dd 33 ?? ad22 ?? o txclk_c_n ? l6n_a0 ac22 ?? o txclk_c_p ? l6p_a0 l16 ?? v ss v ss ?? m11 ?? v ss v ss ?? m12 ?? v ss v ss ?? ae23 ?? idautrec ?? ad23 ?? itstclk ?? af24 ?? v dd 33 v dd 33 ?? ae24 ?? itestrst ?? ae26 ?? i tstshftld ?? m13 ?? v ss v ss ?? d6 ?? v dd 15 v dd 15 ?? f23 ?? v dd 15 v dd 15 ?? m14 ?? v ss v ss ?? m15 ?? v ss v ss ?? ab23 ?? v dd 33 v dd 33 ?? ac24 ?? i resettx ?? ad25 ?? i etoggle ?? ad26 ?? iecsel ?? m16 ?? v ss v ss ?? ac25 ?? iexdnup ?? ac26 ?? imreset ?? ab24 ?? irxd_c0_n ? l7n_a0 aa24 ?? i rxd_c0_p ? l7p_a0 n11 ?? v ss v ss ?? ab25 ?? irxd_c1_n ? l8n_a0
agere systems inc. 83 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair ab26 ?? i rxd_c1_p ? l8p_a0 y23 ?? ilvctap_c_0 ?? y24 ?? i rxd_c2_n ? l9n_a0 y25 ?? i rxd_c2_p ? l9p_a0 n12 ?? v ss v ss ?? aa25 ?? i rxd_c3_n ? l10n_a0 aa26 ?? i rxd_c3_p ? l10p_a0 w24 ?? ilvctap_c_1 ?? y26 ?? i rxsoc_c_n ? l11n_a0 w26 ?? irxsoc_c_p ? l11p_a0 n13 ?? v ss v ss ?? v23 ?? i rxclk_c_n ? l12n_a0 v24 ?? i rxclk_c_p ? l12p_a0 w25 ?? ilvctap_c_2 ?? n14 ?? v ss v ss ?? f4 ?? v dd 15 v dd 15 ?? n15 ?? v ss v ss ?? u24 ?? v dd a_stm v dd a_stm ?? u23 ?? v ss a_stm v ss a_stm ?? n16 ?? v ss v ss ?? v25 ?? i sys_clk_n ? l13n_a0 v26 ?? i sys_clk_p ? l13p_a0 u25 ?? v dd 33 v dd 33 ?? u26 ?? i lvctap_sk ?? p11 ?? v ss v ss ?? t24 ?? i rxd_b0_n ? l14n_a0 t25 ?? i rxd_b0_p ? l14p_a0 p12 ?? v ss v ss ?? t26 ?? i rxd_b1_n ? l15n_a0 r26 ?? i rxd_b1_p ? l15p_a0 l23 ?? v dd 15 v dd 15 ?? r23 ?? i lvctap_b_0 ?? r24 ?? i rxd_b2_n ? l16n_a0 r25 ?? i rxd_b2_p ? l16p_a0 p13 ?? v ss v ss ?? p26 ?? i rxd_b3_n ? l17n_a0 p25 ?? i rxd_b3_p ? l17p_a0 p24 ?? i lvctap_b_1 ?? p14 ?? v ss v ss ?? n26 ?? v dd 33 v dd 33 ?? p15 ?? v ss v ss ?? l4 ?? v dd 15 v dd 15 ??
84 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair p16 ?? v ss v ss ?? r11 ?? v ss v ss ?? n24 ?? ireslo ?? n23 ?? ireshi ?? n25 ?? iref14 ?? m26 ?? iref10 ?? m25 ?? v dd 33 v dd 33 ?? r12 ?? v ss v ss ?? m24 ?? o txd_b0_n ? l18n_a0 m23 ?? o txd_b0_p ? l18p_a0 l26 ?? o txd_b1_n ? l19n_a0 k26 ?? o txd_b1_p ? l19p_a0 r13 ?? v ss v ss ?? l25 ?? o txd_b2_n ? l20n_a0 l24 ?? o txd_b2_p ? l20p_a0 k25 ?? o txd_b3_n ? l21n_a0 k24 ?? o txd_b3_p ? l21p_a0 r14 ?? v ss v ss ?? j26 ?? v dd 33 v dd 33 ?? j25 ?? igclk_n ? l22n_d0 h26 ?? igclk_p ? l22p_d0 g26 ?? v dd 33 v dd 33 ?? k23 ?? ilvctap_gk ?? j24 ?? v dd a_shim v dd a_shim ?? f26 ?? v ss a_shim v ss a_shim ?? h25 ?? irxd_a0_n ? l23n_a0 g25 ?? irxd_a0_p ? l23p_a0 h24 ?? irxd_a1_n ? l24n_a0 h23 ?? irxd_a1_p ? l24p_a0 e26 ?? i lvctap_a_0 ?? e25 ?? v dd 33 v dd 33 ?? g24 ?? irxsoc_a_n ? l25n_a0 g23 ?? i rxsoc_a_p ? l25p_a0 f25 ?? i rxclk_a_n ? l26n_a0 f24 ?? i rxclk_a_p ? l26p_a0 d26 ?? i lvctap_a_2 ?? c26 ?? v dd 33 v dd 33 ?? d25 ?? o tstmux0s ?? e24 ?? o tstmux1s ?? c25 ?? o tstmux2s ?? e23 ?? o tstmux3s ?? d24 ?? o tstmux4s ??
agere systems inc. 85 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair a25 ?? v dd 33 v dd 33 ?? b24 ?? o tstmux5s ?? a24 ?? v dd 33 v dd 33 ?? c23 ?? o tstmux6s ?? b23 ?? o tstmux7s ?? a23 ?? o tstmux8s ?? d22 ?? o tstmux9s ?? c22 ?? v dd 33 v dd 33 ?? a22 ?? i scanen ?? b22 ?? i scan_tstmd ?? c21 ?? irst_n ?? b21 ?? o txd_a0_n ? l27n_a0 a21 ?? otxd_a0_p ? l27p_a0 d20 ?? o txd_a1_n ? l28n_a0 c20 ?? otxd_a1_p ? l28p_a0 b20 ?? o txsoc_a_n ? l29n_a0 a20 ?? o txsoc_a_p ? l29p_a0 c19 ?? o txclk_a_n ? l30n_a0 b19 ?? o txclk_a_p ? l30p_a0 a19 ?? v dd 33 v dd 33 ?? r15 ?? v ss v ss ?? d18 1 (tc) 1 io pt26d ? l1c_a0 c18 1 (tc) 1 io pt26c ? l1t_a0 b18 1 (tc) 1 io pt25d vref_1_01 l2c_a0 a18 1 (tc) 1 io pt25c ? l2t_a0 r16 ?? v ss v ss ?? d17 1 (tc) 1 io pt25b ? l3c_a0 c17 1 (tc) 1 io pt25a ? l3t_a0 b17 1 (tc) 2 io pt24d ? l4c_a0 a17 1 (tc) 2 io pt24c vref_1_02 l4t_a0 c16 1 (tc) ? v dd io1 v dd io1 ?? b16 1 (tc) 2 io pt23d ? l5c_a0 a16 1 (tc) 2 io pt23c ? l5t_a0 t11 ?? v ss v ss ?? d15 1 (tc) 3 io pt22d ? l6c_a0 c15 1 (tc) 3 io pt22c vref_1_03 l6t_a0 t23 ?? v dd 15 v dd 15 ?? b15 1 (tc) 3 io pt21d ? l7c_a0 a15 1 (tc) 3 io pt21c ? l7t_a0 t12 ?? v ss v ss ?? c14 1 (tc) 4 io pt19d ? l8c_a0 b14 1 (tc) 4 io pt19c ? l8t_a0
86 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair t13 ?? v ss v ss ?? c13 1 (tc) 4 io pt18d ? l9c_a0 d13 1 (tc) 4 io pt18c vref_1_04 l9t_a0 a14 1 (tc) ? v dd io1 v dd io1 ?? b13 1 (tc) 5 io pt17d ptck1c l10c_a0 a13 1 (tc) 5 io pt17c ptck1t l10t_a0 t14 ?? v ss v ss ?? c12 1 (tc) 5 io pt16d ptck0c l11c_a0 d12 1 (tc) 5 io pt16c ptck0t l11t_a0 t4 ?? v dd 15 v dd 15 ?? b12 1 (tc) 5 io pt15d vref_1_05 l12c_a0 a12 1 (tc) 5 io pt15c ? l12t_a0 t15 ?? v ss v ss ?? b11 1 (tc) 6 io pt13d ? l13c_a0 c11 1 (tc) 6 io pt13c vref_1_06 l13t_a0 t16 ?? v ss v ss ?? a11 0 (tl) 1 io pt11d mpi_rtry_n l1c_a0 a10 0 (tl) 1 io pt11c mpi_ack_n l1c_a0 b10 0 (tl) ? v dd io0 v dd io0 ?? c10 0 (tl) 1 io pt10d m0 l2c_a0 d10 0 (tl) 1 io pt10c m1 l2t_a0 b9 0 (tl) 2 io pt10b mpi_clk l3c_a0 c9 0 (tl) 2 io pt10a a21/mpi_burst_n l3c_a0 a9 0 (tl) 2 io pt9d m2 l4c_d0 b8 0 (tl) 2 io pt9c m3 l4t_d0 a8 0 (tl) 2 io pt9b vref_0_02 l5c_a0 a7 0 (tl) 2 io pt9a mpi_tea_n l5t_a0 c8 0 (tl) 3 io pt7d d0 l6c_a0 d8 0 (tl) 3 io pt7c tms l6t_a0 ac18 ?? v ss v ss ?? b7 0 (tl) 4 io pt7b a20/mpi_bdip_n l7c_a0 c7 0 (tl) 4 io pt7a a19/mpi_tsz1 l7t_a0 b6 0 (tl) 4 io pt6d a18/mpi_tsz0 l8c_a0 c6 0 (tl) 4 io pt6c d3 l8t_a0 d7 0 (tl) ? v dd io0 v dd io0 ?? a6 0 (tl) 5 io pt5d d1 l9c_a0 a5 0 (tl) 5 io pt5c d2 l9t_a0 ac23 ?? v ss v ss ?? b5 0 (tl) 5 io pt4d tdi l10c_a0 c5 0 (tl) 5 io pt4c tck l10t_a0 a4 0 (tl) 6 io pt3c vref_0_06 ? ac4 ?? v ss v ss ??
agere systems inc. 87 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 33. ort8850l 352-pin pbga pinout (continued) ba352 v dd io bank vref group i/o ort8850l additional function pair b4 0 (tl) 6 io pt2d pll_ck1c/ppll l11c_a0 c4 0 (tl) 6 io pt2c pll_ck1t/ppll l11t_a0 a3 ?? o pcfg_mpi_irq cfg_irq_n/mpi_irq_n ? b3 ?? io pcclk cclk ? d3 ?? io pdone done ? d5 ?? v dd 33 v dd 33 ?? ac8 ?? v ss v ss ?? ad24 ?? v ss v ss ?? af26 ?? v ss v ss ?? b2 ?? v ss v ss ??
88 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair a1 ?? v ss v ss v ss ?? e4 ?? v dd 33 v dd 33 v dd 33 ?? f5 ?? o prd_data prd_data rd_data/tdo ? d2 ?? i preset_n preset_n reset_n ? e3 ?? i prd_cfg_n prd_cfg_n rd_cfg_n ? g5 ?? i pprgrm_n pprgrm_n prgrm_n ? c4 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? f4 0 (tl) 7 io pl2d pl2d pll_ck0c/hppll l21c_d2 d1 0 (tl) 7 io pl2c pl2c pll_ck0t/hppll l21t_d2 a2 ?? v ss v ss v ss ?? e2 0 (tl) 7 io pl2b pl3d ? l22c_d0 f3 0 (tl) 7 io pl2a pl3c vref_0_07 l22t_d0 g4 0 (tl) 7 io pl3d pl4d d5 l23c_d0 h5 0 (tl) 7 io pl3c pl4c d6 l23t_d0 d3 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? e1 0 (tl) 8 io pl3b pl5d ? l24c_d0 f2 0 (tl) 8 io pl3a pl5c vref_0_08 l24t_d0 j5 0 (tl) 8 io pl4d pl6d hdc l25c_d1 g3 0 (tl) 8 io pl4c pl6c ldc_n l25t_d1 a18 ?? v ss v ss v ss ?? h4 0 (tl) 8 io pl4b pl7d ? l26c_d2 f1 0 (tl) 8 io pl4a pl7c ? l26t_d2 g2 0 (tl) 9 io pl5d pl8d testcfg l27c_d0 h3 0 (tl) 9 io pl5c pl8c d7 l27t_d0 e5 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? k5 0 (tl) 9 io pl5b pl9d vref_0_09 l28c_d0 j4 0 (tl) 9 io pl5a pl9c a17/ppc_a31 l28t_d0 g1 0 (tl) 9 io pl6d pl10d cs0_n l29c_d3 l5 0 (tl) 9 io pl6c pl10c cs1 l29t_d3 a33 ?? v ss v ss v ss ?? h2 0 (tl) 10 io pl6b pl11d ? l30c_d0 j3 0 (tl) 10 io pl6a pl11c ? l30t_d0 h1 0 (tl) 10 io pl7d pl12d init_n l31c_d0 j2 0 (tl) 10 io pl7c pl12c dout l31t_d0 k3 0 (tl) 10 io pl7b pl13d vref_0_10 l32c_d0 l4 0 (tl) 10 io pl7a pl13c a16/ppc_a30 l32t_d0 j1 7 (cl) 1 io pl8d pl14d a15/ppc_a29 l1c_d0 k2 7 (cl) 1 io pl8c pl14c a14/ppc_a28 l1t_d0 l1 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? m4 7 (cl) 1 io pl8b pl15d ? l2c_d0 l3 7 (cl) 1 io pl8a pl15c ? l2t_d0 k1 7 (cl) 1 io pl9d pl16d vref_7_01 l3c_d3
agere systems inc. 89 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair n5 7 (cl) 1 io pl9c pl16c d4 l3t_d3 am22 ?? v ss v ss v ss ?? l2 7 (cl) 2 io pl9b pl17d ? l4c_d1 n4 7 (cl) 2 io pl9a pl17c ? l4t_d1 p5 7 (cl) 2 io pl10d pl18d rdy/busy_n/rclk l5c_d2 m2 7 (cl) 2 io pl10c pl18c vref_7_02 l5t_d2 m3 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? m1 7 (cl) 2 io pl10b pl19d a13/ppc_a27 l6c_d2 p4 7 (cl) 2 io pl10a pl19c a12/ppc_a26 l6t_d2 n2 7 (cl) 3 io pl11d pl20d ? l7c_d0 p3 7 (cl) 3 io pl11c pl20c ? l7t_d0 am32 ?? v ss v ss v ss ?? r4 7 (cl) 3 io pl11b pl21d a11/ppc_a25 l8c_d2 n1 7 (cl) 3 io pl11a pl21c vref_7_03 l8t_d2 p2 7 (cl) 3 io pl12d pl22d ? l9c_a0 p1 7 (cl) 3 io pl12c pl22c ? l9t_a0 t4 7 (cl) 3 io pl12b pl22b ? l10c_d1 r2 7 (cl) 3 io pl12a pl22a ? l10t_d1 u5 7 (cl) 4 io pl13d pl23d rd_n/mpi_strb_n l11c_d3 r1 7 (cl) 4 io pl13c pl23c vref_7_04 l11t_d3 an1 ?? v ss v ss v ss ?? v5 7 (cl) 4 io pl13b pl23b ? l12c_d1 t3 7 (cl) 4 io pl13a pl23a ? l12t_d1 t2 7 (cl) 4 io pl14d pl24d plck0c l13c_a0 t1 7 (cl) 4 io pl14c pl24c plck0t l13t_a0 r3 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? u4 7 (cl) 4 io pl14b pl24b ? l14c_a0 u3 7 (cl) 4 io pl14a pl24a ? l14t_a0 an2 ?? v ss v ss v ss ?? u2 7 (cl) 5 io pl15d pl25d a10/ppc_a24 l15c_a0 v2 7 (cl) 5 io pl15c pl25c a9/ppc_a23 l15t_a0 an33 ?? v ss v ss v ss ?? v3 7 (cl) 5 io pl15b pl25b ? l16c_a0 v4 7 (cl) 5 io pl15a pl25a ? l16t_a0 w5 7 (cl) 5 io pl16d pl26d a8/ppc_a22 l17c_a2 w2 7 (cl) 5 io pl16c pl26c vref_7_05 l17t_a2 w3 7 (cl) 5 io pl16b pl27d ? l18c_d1 y1 7 (cl) 5 io pl16a pl27c ? l18t_d1 y2 7 (cl) 6 io pl17d pl28d plck1c l19c_d0 aa1 7 (cl) 6 io pl17c pl28c plck1t l19t_d0 an34 ?? v ss v ss v ss ?? y5 7 (cl) 6 io pl17b pl29d vref_7_06 l20c_d3
90 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair ab1 7 (cl) 6 io pl17a pl29c a7/ppc_a21 l20t_d3 aa5 7 (cl) 6 io pl18d pl30d a6/ppc_a20 l21c_a1 aa3 7 (cl) 6 io pl18c pl30c a5/ppc_a19 l21t_a1 u1 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? ab2 7 (cl) 7 io pl18b pl31d ?? aa4 7 (cl) 7 io pl19d pl32d wr_n/mpi_rw l22c_d2 ac1 7 (cl) 7 io pl19c pl32c vref_7_07 l22t_d2 ab5 7 (cl) 7 io pl19b pl33d ? l23c_d2 ac2 7 (cl) 7 io pl19a pl33c ? l23t_d2 ab4 7 (cl) 8 io pl20d pl34d a4/ppc_a18 l23c_d0 ac5 7 (cl) 8 io pl20c pl34c vref_7_08 l23t_d0 w1 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? ad2 7 (cl) 8 io pl20b pl35d a3/ppc_a17 l23c_d0 ae1 7 (cl) 8 io pl20a pl35c a2/ppc_a16 l23t_d0 ad3 7 (cl) 8 io pl21d pl36d a1/ppc_a15 l24c_d0 ae2 7 (cl) 8 io pl21c pl36c a0/ppc_a14 l24t_d0 af1 7 (cl) 8 io pl21b pl37d dp0 l25c_d2 ad4 7 (cl) 8 io pl21a pl37c dp1 l25t_d2 ae3 6 (bl) 1 io pl22d pl38d d8 l1c_d0 af2 6 (bl) 1 io pl22c pl38c vref_6_01 l1t_d0 ab13 ?? v ss v ss v ss ?? ae4 6 (bl) 1 io pl22b pl39d d9 l2c_d0 af3 6 (bl) 1 io pl22a pl39c d10 l2t_d0 ae5 6 (bl) 2 io pl23d pl40d ? l3c_d1 ag2 6 (bl) 2 io pl23c pl40c vref_6_02 l3t_d1 ak5 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? ah1 6 (bl) 2 io pl23b pl41d ? l4c_d3 af5 6 (bl) 2 io pl23a pl41c ? l4t_d3 af4 6 (bl) 3 io pl24d pl42d d11 l5c_d0 ag3 6 (bl) 3 io pl24c pl42c d12 l5t_d0 ab14 ?? v ss v ss v ss ?? ah2 6 (bl) 3 io pl24b pl43d ? l6c_d0 aj1 6 (bl) 3 io pl24a pl43c ? l6t_d0 ag4 6 (bl) 3 io pl25d pl44d vref_6_03 l7c_a0 ag5 6 (bl) 3 io pl25c pl44c d13 l7t_a0 al3 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? ah3 6 (bl) 4 io pl25b pl44b ?? ak1 6 (bl) 4 io pl25a pl45a ?? aj2 6 (bl) 4 io pl26d pl45d ? l8c_d2 ah5 6 (bl) 4 io pl26c pl45c vref_6_04 l8t_d2 ab15 ?? v ss v ss v ss ?? ah4 6 (bl) 4 io pl26b pl46d ??
agere systems inc. 91 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair aj3 6 (bl) 4 io pl26a pl46a ?? ak2 6 (bl) 4 io pl27d pl47d pll_ck7c/hppll l9c_d0 al1 6 (bl) 4 io pl27c pl47c pll_ck7t/hppll l9t_d0 ab20 ?? v ss v ss v ss ?? aj5 6 (bl) 4 io pl27b pl47b ? l10c_a0 aj4 6 (bl) 4 io pl27a pl47a ? l10t_a0 ab21 ?? v ss v ss v ss ?? ak3 ?? i ptemp ptemp ptemp ? am1 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? al2 ?? io lvds_r lvds_r lvds_r ? ak4 ?? v dd 33 v dd 33 v dd 33 ?? ab22 ?? v ss v ss v ss ?? ak6 ?? v dd 33 v dd 33 v dd 33 ?? al5 6 (bl) 5 io pb2a pb2a dp2 l11t_d1 an4 6 (bl) 5 io pb2b pb2b ? l11c_d1 am2 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? am5 6 (bl) 5 io pb2c pb2c pll_ck6t/ppll l12t_d1 ak7 6 (bl) 5 io pb2d pb2d pll_ck6c/ppll l12c_d1 al6 6 (bl) 5 io pb3a pb3c ? l13t_d1 an5 6 (bl) 5 io pb3b pb3d ? l13c_d1 am4 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? am6 6 (bl) 5 io pb3c pb4c vref_6_05 l14t_d0 al7 6 (bl) 5 io pb3d pb4d dp3 l14c_d0 ak8 6 (bl) 6 io pb4a pb5c ? l15t_d3 ap5 6 (bl) 6 io pb4b pb5d ? l15c_d3 ab32 ?? v ss v ss v ss ?? ak9 6 (bl) 6 io pb4c pb6c vref_6_06 l16t_d2 an6 6 (bl) 6 io pb4d pb6d d14 l16c_d2 am7 6 (bl) 6 io pb5a pb7c ? l17t_d1 ap6 6 (bl) 6 io pb5b pb7d ? l17c_d1 an3 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? al8 6 (bl) 7 io pb5c pb8c d15 l18t_d1 an7 6 (bl) 7 io pb5d pb8d d16 l18c_d1 am8 6 (bl) 7 io pb6a pb9c d17 l19t_d0 al9 6 (bl) 7 io pb6b pb9d d18 l19c_d0 al4 ?? v ss v ss v ss ?? ap7 6 (bl) 7 io pb6c pb10c vref_6_07 l20t_d0 an8 6 (bl) 7 io pb6d pb10d d19 l20c_d0 al10 6 (bl) 8 io pb7a pb11c d20 l21t_d2 ap8 6 (bl) 8 io pb7b pb11d d21 l21c_d2 al11 6 (bl) 8 io pb7c pb12c vref_6_08 l22t_d0 am10 6 (bl) 8 io pb7d pb12d d22 l22c_d0
92 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair ak12 6 (bl) 9 io pb8a pb13a ? l23t_d3 ap9 6 (bl) 9 io pb8b pb13b ? l23c_d3 al31 ?? v ss v ss v ss ?? an10 6 (bl) 9 io pb8c pb13c d23 l24t_d1 al12 6 (bl) 9 io pb8d pb13d d24 l24c_d1 am11 6 (bl) 9 io pb9a pb14a ? l25t_d1 ap10 6 (bl) 9 io pb9b pb14b ? l25c_d1 ap3 6 (bl) ? v dd io6 v dd io6 v dd io6 ?? ak13 6 (bl) 9 io pb9c pb14c vref_6_09 l26t_d2 an11 6 (bl) 9 io pb9d pb14d d25 l26c_d2 al13 6 (bl) 9 io pb10a pb15c ? l27t_d0 ak14 6 (bl) 9 io pb10b pb15d ? l27c_d0 am3 ?? v ss v ss v ss ?? an12 6 (bl) 10 io pb10c pb16c d26 l28t_d1 al14 6 (bl) 10 io pb10d pb16d d27 l28c_d1 ap12 6 (bl) 10 io pb11a pb17c ? l29t_d0 an13 6 (bl) 10 io pb11b pb17d ? l29c_d0 ap13 6 (bl) 10 io pb11c pb18c vref_6_10 l30t_d3 ak15 6 (bl) 10 io pb11d pb18d d28 l30c_d3 al15 6 (bl) 11 io pb12a pb19c d29 l31t_d0 ak16 6 (bl) 11 io pb12b pb19d d30 l31c_d0 am13 ?? v ss v ss v ss ?? ap14 6 (bl) 11 io pb12c pb20c vref_6_11 l32t_d2 al16 6 (bl) 11 io pb12d pb20d d31 l32c_d2 an15 5 (bc) 1 io pb13c pb21a ?? ap15 5 (bc) 1 io pb14a pb21c ? l1t_d3 ak17 5 (bc) 1 io pb14b pb21d ? l1c_d3 y15 ?? v ss v ss v ss ?? am16 5 (bc) 1 io pb14c pb22a ?? an16 5 (bc) 1 io pb15a pb22c vref_5_01 l2t_d1 al17 5 (bc) 1 io pb15b pb22d ? l2c_d1 am12 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? ap16 5 (bc) 2 io pb15c pb23a ? l3t_d1 am17 5 (bc) 2 io pb15d pb23b ? l3c_d1 an17 5 (bc) 2 io pb16a pb23c pbck0t l4t_d1 al18 5 (bc) 2 io pb16b pb23d pbck0c l4c_d1 an18 5 (bc) 2 io pb16c pb24a ? l5t_a0 am18 5 (bc) 2 io pb16d pb24b ? l5c_a0 an19 5 (bc) 2 io pb17a pb24c vref_5_02 l6t_d2 ak18 5 (bc) 2 io pb17b pb24d ? l6c_d2 y20 ?? v ss v ss v ss ?? am19 5 (bc) 2 io pb17c pb25c ? l7t_a0
agere systems inc. 93 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair al19 5 (bc) 2 io pb17d pb25d ? l7c_a0 ap20 5 (bc) 3 io pb18a pb26c ? l8t_d3 ak19 5 (bc) 3 io pb18b pb26d vref_5_03 l8c_d3 am15 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? an20 5 (bc) 3 io pb18c pb27a ?? y21 ?? v ss v ss v ss ?? ap21 5 (bc) 3 io pb19a pb27c ? l9t_d2 al20 5 (bc) 3 io pb19b pb27d ? l9c_d2 y22 ?? v ss v ss v ss ?? ak20 5 (bc) 3 io pb19c pb28a ?? an21 5 (bc) 3 io pb20a pb28c pbck1t l10t_a0 am21 5 (bc) 3 io pb20b pb28d pbck1c l10c_a0 am20 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? ak21 5 (bc) 3 io pb20c pb29a ?? ap22 5 (bc) 4 io pb21a pb29c ? l11t_d2 al21 5 (bc) 4 io pb21b pb29d ? l11c_d2 aa15 ?? v ss v ss v ss ?? an22 5 (bc) 4 io pb21c pb30a ?? ap23 5 (bc) 4 io pb22a pb30c ? l12t_a0 an23 5 (bc) 4 io pb22b pb30d vref_5_04 l12c_a0 aa13 ?? v ss v ss v ss ?? ak22 5 (bc) 4 io pb22c pb31c ? l13t_a0 al22 5 (bc) 4 io pb22d pb31d ? l13c_a0 an24 5 (bc) 5 io pb23c pb32c ? l14t_d2 ak23 5 (bc) 5 io pb23d pb32d vref_5_05 l14c_d2 aa14 ?? v ss v ss v ss ?? al23 5 (bc) 5 io pb24c pb33c ? l15t_d0 am24 5 (bc) 5 io pb24d pb33d ? l15c_d0 ap25 5 (bc) 5 io pb25a pb34c ? l16t_a0 an25 5 (bc) 5 io pb25b pb34d ? l16t_a0 ap26 5 (bc) 6 io pb25c pb35a ?? ak25 5 (bc) 6 io pb26a pb35c ? l17t_a0 an26 5 (bc) 6 io pb26b pb35d vref_5_06 l17c_a0 ap27 5 (bc) 6 io pb26c pb36a ?? am25 5 (bc) 6 io pb27a pb36c ? l18t_d3 ak26 5 (bc) 6 io pb27b pb36d ? l18c_d3 n32 ?? v ss v ss v ss ?? al24 ?? o txd_c0_n txd_c0_n ? l1n_a0 ak24 ?? o txd_c0_p txd_c0_p ? l1p_a0 a32 ?? v dd 33 v dd 33 v dd 33 ?? an27 ?? o txd_c1_n txd_c1_n ? l2n_d0 ap28 ?? o txd_c1_p txd_c1_p ? l2p_d0
94 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair p13 ?? v ss v ss v ss ?? al25 ?? o txd_c2_n txd_c2_n ? l3n_a0 al26 ?? o txd_c2_p txd_c2_p ? l3p_a0 b32 ?? v dd 33 v dd 33 v dd 33 ?? am26 ?? o txd_c3_n txd_c3_n ? l4n_a0 am27 ?? o txd_c3_p txd_c3_p ? l4p_a0 p14 ?? v ss v ss v ss ?? an28 ?? o txsoc_c_n txsoc_c_n ? l5n_d0 ap29 ?? o txsoc_c_p txsoc_c_p ? l5p_d0 c31 ?? v dd 33 v dd 33 v dd 33 ?? al27 ?? o txclk_c_n txclk_c_n ? l6n_a0 ak27 ?? o txclk_c_p txclk_c_p ? l6p_a0 p15 ?? v ss v ss v ss ?? al28 ?? o txd_c4_n txd_c4_n ? l7n_a0 ak28 ?? o txd_c4_p txd_c4_p ? l7p_a0 c33 ?? v dd 33 v dd 33 v dd 33 ?? am28 ?? o txd_c5_n txd_c5_n ? l8n_d0 an29 ?? o txd_c5_p txd_c5_p ? l8p_d0 p20 ?? v ss v ss v ss ?? al29 ?? o txd_c6_n txd_c6_n ? l9n_a0 ak29 ?? o txd_c6_p txd_c6_p ? l9p_a0 c34 ?? v dd 33 v dd 33 v dd 33 ?? ap30 ?? o txd_c7_n txd_c7_n ? l10n_d0 an30 ?? o txd_c7_p txd_c7_p ? l10p_d0 p21 ?? v ss v ss v ss ?? am29 ?? i dautrec dautrec ?? ap31 ?? i tstclk tstclk ?? d32 ?? v dd 33 v dd 33 v dd 33 ?? am30 ?? i testrst testrst ?? an31 ?? i tstshftld tstshftld ?? p22 ?? v ss v ss v ss ?? r13 ?? v ss v ss v ss ?? r14 ?? v ss v ss v ss ?? e30 ?? v dd 33 v dd 33 v dd 33 ?? al30 ?? i resettx resettx ?? e31 ?? v dd 33 v dd 33 v dd 33 ?? ah30 ?? i etoggle etoggle ?? aj30 ?? i ecsel ecsel ?? r15 ?? v ss v ss v ss ?? al33 ?? i exdnup exdnup ?? ah31 ?? i mreset mreset ?? l34 ?? v dd 33 v dd 33 v dd 33 ??
agere systems inc. 95 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair ak32 ?? i rxd_c0_n rxd_c0_n ? l11n_d0 aj31 ?? i rxd_c0_p rxd_c0_p ? l11p_d0 r20 ?? v ss v ss v ss ?? al34 ?? i rxd_c1_n rxd_c1_n ? l12n_d0 ak33 ?? i rxd_c1_p rxd_c1_p ? l12p_d0 aj32 ?? i lvctap_c_0 lvctap_c_0 ?? m32 ?? v dd 33 v dd 33 v dd 33 ?? af30 ?? i rxd_c2_n rxd_c2_n ? l13n_a0 ag30 ?? i rxd_c2_p rxd_c2_p ? l13p_a0 r21 ?? v ss v ss v ss ?? ag31 ?? i rxd_c3_n rxd_c3_n ? l14n_a0 af31 ?? i rxd_c3_p rxd_c3_p ? l14p_a0 ak34 ?? i lvctap_c_1 lvctap_c_1 ?? r32 ?? v dd 33 v dd 33 v dd 33 ?? aj33 ?? i rxsoc_c_n rxsoc_c_n ? l15n_a0 ah32 ?? i rxsoc_c_p rxsoc_c_p ? l15p_a0 r22 ?? v ss v ss v ss ?? aj34 ?? i rxclk_c_n rxclk_c_n ? l16n_d0 ah33 ?? i rxclk_c_p rxclk_c_p ? l16p_d0 ad30 ?? i lvctap_c_2 lvctap_c_2 ?? u34 ?? v dd 33 v dd 33 v dd 33 ?? ag32 ?? i rxd_c4_n rxd_c4_n ? l17n_a0 ag33 ?? i rxd_c4_p rxd_c4_p ? l17p_a0 t16 ?? v ss v ss v ss ?? ah34 ?? i lvctap_c_3 lvctap_c_3 ?? ae30 ?? i rxd_c5_n rxd_c5_n ? l18n_a0 ae31 ?? i rxd_c5_p rxd_c5_p ? l18p_a0 w34 ?? v dd 33 v dd 33 v dd 33 ?? af32 ?? i rxd_c6_n rxd_c6_n ? l19n_a0 af33 ?? i rxd_c6_p rxd_c6_p ? l19p_a0 t17 ?? v ss v ss v ss ?? ac30 ?? i lvctap_c_4 lvctap_c_4 ?? ag34 ?? i rxd_c7_n rxd_c7_n ? l20n_a0 af34 ?? i rxd_c7_p rxd_c7_p ? l20p_a0 y32 ?? v dd 33 v dd 33 v dd 33 ?? ab30 ?? v dd a_stm v dd a_stm v dd a_stm ?? ad31 ?? v ss a_stm v ss a_stm v ss a_stm ?? t18 ?? v ss v ss v ss ?? ae32 ?? i sys_clk_n sys_clk_n ? l21n_d0 ae33 ?? i sys_clk_p sys_clk_p ? l21p_d0 ac32 ?? v dd 33 v dd 33 v dd 33 ?? ae34 ?? i lvctap_sk lvctap_sk ??
96 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair t19 ?? v ss v ss v ss ?? ac31 ?? i rxd_b0_n rxd_b0_n ? l22n_a0 ab31 ?? i rxd_b0_p rxd_b0_p ? l22p_a0 t34 ?? v ss v ss v ss ?? ad32 ?? i rxd_b1_n rxd_b1_n ? l23n_a0 ad33 ?? i rxd_b1_p rxd_b1_p ? l23p_a0 aa30 ?? i lvctap_b_0 lvctap_b_0 ?? ad34 ?? v dd 33 v dd 33 v dd 33 ?? ac33 ?? i rxd_b2_n rxd_b2_n ? l24n_a0 ac34 ?? i rxd_b2_p rxd_b2_p ? l24p_a0 u16 ?? v ss v ss v ss ?? ab33 ?? i rxd_b3_n rxd_b3_n ? l25n_a0 ab34 ?? i rxd_b3_p rxd_b3_p ? l25p_a0 y30 ?? i lvctap_b_1 lvctap_b_1 ?? ak30 ?? v dd 33 v dd 33 v dd 33 ?? aa31 ?? i rxsoc_b_n rxsoc_b_n ? l26n_a0 aa32 ?? i rxsoc_b_p rxsoc_b_p ? l26p_a0 u17 ?? v ss v ss v ss ?? w30 ?? i rxclk_b_n rxclk_b_n ? l27n_d0 y31 ?? i rxclk_b_p rxclk_b_p ? l27p_d0 aa33 ?? i lvctap_b_2 lvctap_b_2 ?? ak31 ?? v dd 33 v dd 33 v dd 33 ?? aa34 ?? i rxd_b4_n rxd_b4_n ? l28n_a0 y34 ?? i rxd_b4_p rxd_b4_p ? l28p_a0 u18 ?? v ss v ss v ss ?? y33 ?? i lvctap_b_3 lvctap_b_3 ?? w31 ?? i rxd_b5_n rxd_b5_n ? l29n_a0 w32 ?? i rxd_b5_p rxd_b5_p ? l29p_a0 al32 ?? v dd 33 v dd 33 v dd 33 ?? v30 ?? i rxd_b6_n rxd_b6_n ? l30n_a0 v31 ?? i rxd_b6_p rxd_b6_p ? l30p_a0 u19 ?? v ss v ss v ss ?? w33 ?? i lvctap_b_4 lvctap_b_4 ?? v32 ?? i rxd_b7_n rxd_b7_n ? l31n_a0 v33 ?? i rxd_b7_p rxd_b7_p ? l31p_a0 v1 ?? v ss v ss v ss ?? u33 ?? iresloreslo ?? u32 ?? i reshi reshi ?? u31 ?? iref14ref14 ?? t33 ?? iref10ref10 ?? am31 ?? v dd 33 v dd 33 v dd 33 ?? v16 ?? v ss v ss v ss ??
agere systems inc. 97 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair t32 ?? o txd_b0_n txd_b0_n ? l32n_d1 r34 ?? o txd_b0_p txd_b0_p ? l32p_d1 am33 ?? v dd 33 v dd 33 v dd 33 ?? u30 ?? o txd_b1_n txd_b1_n ? l33n_d0 t31 ?? o txd_b1_p txd_b1_p ? l33p_d0 v17 ?? v ss v ss v ss ?? r33 ?? o txd_b2_n txd_b2_n ? l34n_d0 p34 ?? o txd_b2_p txd_b2_p ? l34p_d0 am34 ?? v dd 33 v dd 33 v dd 33 ?? p33 ?? o txd_b3_n txd_b3_n ? l35n_d0 n34 ?? o txd_b3_p txd_b3_p ? l35p_d0 v18 ?? v ss v ss v ss ?? t30 ?? o txsoc_b_n txsoc_b_n ? l36n_d0 r31 ?? o txsoc_b_p txsoc_b_p ? l36p_d0 an32 ?? v dd 33 v dd 33 v dd 33 ?? p32 ?? o txclk_b_n txclk_b_n ? l37n_d1 r30 ?? o txclk_b_p txclk_b_p ? l37p_d1 v19 ?? v ss v ss v ss ?? n33 ?? o txd_b4_n txd_b4_n ? l38n_d0 m34 ?? o txd_b4_p txd_b4_p ? l38p_d0 ap32 ?? v dd 33 v dd 33 v dd 33 ?? p31 ?? o txd_b5_n txd_b5_n ? l39n_d1 m33 ?? o txd_b5_p txd_b5_p ? l39p_d1 v34 ?? v ss v ss v ss ?? n31 ?? o txd_b6_n txd_b6_n ? l40n_d0 p30 ?? o txd_b6_p txd_b6_p ? l40p_d0 l33 ?? o txd_b7_n txd_b7_n ? l41n_d0 k34 ?? o txd_b7_p txd_b7_p ? l41p_d0 w16 ?? v ss v ss v ss ?? m31 ?? igclk_ngclk_n ? l42n_d0 l32 ?? i gclk_p gclk_p ? l42p_d0 k33 ?? i lvctap_gk lvctap_gk ?? w17 ?? v ss v ss v ss ?? n30 ?? v dd a_shim v dd a_shim v dd a_shim ?? l30 ?? v ss a_shim v ss a_shim v ss a_shim ?? w18 ?? v ss v ss v ss ?? m30 ?? i rxd_a0_n rxd_a0_n ? l43n_d0 l31 ?? i rxd_a0_p rxd_a0_p ? l43p_d0 w19 ?? v ss v ss v ss ?? j34 ?? i rxd_a1_n rxd_a1_n ? l44n_d1 k32 ?? i rxd_a1_p rxd_a1_p ? l44p_d1 j33 ?? i lvctap_a_0 lvctap_a_0 ??
98 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair h34 ?? i rxd_a2_n rxd_a2_n ? l45n_d1 j32 ?? i rxd_a2_p rxd_a2_p ? l45p_d1 y13 ?? v ss v ss v ss ?? k31 ?? i rxd_a3_n rxd_a3_n ? l46n_a0 k30 ?? i rxd_a3_p rxd_a3_p ? l46p_a0 h33 ?? i lvctap_a_1 lvctap_a_1 ?? j31 ?? i rxsoc_a_n rxsoc_a_n ? l47n_a0 j30 ?? i rxsoc_a_p rxsoc_a_p ? l47p_a0 y14 ?? v ss v ss v ss ?? g34 ?? i rxclk_a_n rxclk_a_n ? l48n_d1 h32 ?? i rxclk_a_p rxclk_a_p ? l48p_d1 h31 ?? i lvctap_a_2 lvctap_a_2 ?? g33 ?? i rxd_a4_n rxd_a4_n ? l49n_d0 f34 ?? i rxd_a4_p rxd_a4_p ? l49p_d0 h30 ?? i lvctap_a_3 lvctap_a_3 ?? g32 ?? i rxd_a5_n rxd_a5_n ? l50n_d0 f33 ?? i rxd_a5_p rxd_a5_p ? l50p_d0 g30 ?? i rxd_a6_n rxd_a6_n ? l51n_a0 g31 ?? i rxd_a6_p rxd_a6_p ? l51p_a0 e34 ?? i lvctap_a_4 lvctap_a_4 ?? f32 ?? i rxd_a7_n rxd_a7_n ? l52n_a0 e33 ?? i rxd_a7_p rxd_a7_p ? l52p_a0 f31 ?? o tstmux0s tstmux0s ?? e32 ?? o tstmux1s tstmux1s ?? d34 ?? o tstmux2s tstmux2s ?? d33 ?? o tstmux3s tstmux3s ?? f30 ?? o tstmux4s tstmux4s ?? d30 ?? o tstmux5s tstmux5s ?? e29 ?? o tstmux6s tstmux6s ?? c30 ?? o tstmux7s tstmux7s ?? b31 ?? o tstmux8s tstmux8s ?? d29 ?? o tstmux9s tstmux9s ?? b30 ?? i scanen scanen ?? a31 ?? i scan_tstmd scan_tstmd ?? b29 ?? irst_nrst_n ?? e28 ?? o txd_a0_n txd_a0_n ? l53n_d1 c29 ?? o txd_a0_p txd_a0_p ? l53p_d1 d28 ?? o txd_a1_n txd_a1_n ? l54n_d0 e27 ?? o txd_a1_p txd_a1_p ? l54p_d0 a30 ?? o txd_a2_n txd_a2_n ? l55n_d1 c28 ?? o txd_a2_p txd_a2_p ? l55p_d1 b28 ?? o txd_a3_n txd_a3_n ? l56n_d0
agere systems inc. 99 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair a29 ?? o txd_a3_p txd_a3_p ? l56p_d0 d27 ?? o txsoc_a_n txsoc_a_n ? l57n_d0 e26 ?? o txsoc_a_p txsoc_a_p ? l57p_d0 c27 ?? o txclk_a_n txclk_a_n ? l58n_d0 d26 ?? o txclk_a_p txclk_a_p ? l58p_d0 a28 ?? o txd_a4_n txd_a4_n ? l59n_d0 b27 ?? o txd_a4_p txd_a4_p ? l59p_d0 c26 ?? o txd_a5_n txd_a5_n ? l60n_d0 d25 ?? o txd_a5_p txd_a5_p ? l60p_d0 a27 ?? o txd_a6_n txd_a6_n ? l61n_d0 b26 ?? o txd_a6_p txd_a6_p ? l61p_d0 d24 ?? o txd_a7_n txd_a7_n ? l62n_d0 c25 ?? o txd_a7_p txd_a7_p ? l62p_d0 c22 ?? v ss v ss v ss ?? a26 1 (tc) 1 io pt26d pt35d ? l1c_d3 e25 1 (tc) 1 io pt26c pt35c ? l1t_d3 a25 1 (tc) 1 io pt26b pt35b ? l2c_a0 b25 1 (tc) 1 io pt26a pt35a ? l2t_a0 c24 1 (tc) 1 io pt25d pt34d vref_1_01 l3c_d0 d23 1 (tc) 1 io pt25c pt34c ? l3t_d0 c32 ?? v ss v ss v ss ?? b24 1 (tc) 1 io pt25b pt33d ? l4c_a2 e24 1 (tc) 1 io pt25a pt33c ? l4t_a2 d22 1 (tc) 2 io pt24d pt32d ? l5c_d1 b23 1 (tc) 2 io pt24c pt32c vref_1_02 l5t_d1 e23 1 (tc) 2 io pt24b pt31d ? l6c_a3 a23 1 (tc) 2 io pt24a pt31c ? l6t_a3 d21 1 (tc) 2 io pt23d pt30d ? l7c_d1 b22 1 (tc) 2 io pt23c pt30c ? l7t_d1 d4 ?? v ss v ss v ss ?? a22 1 (tc) 3 io pt22d pt29d ? l8c_d1 c21 1 (tc) 3 io pt22c pt29c vref_1_03 l8t_d1 e22 1 (tc) 3 io pt22a pt29a ?? d20 1 (tc) 3 io pt21d pt28d ? l9c_d1 b21 1 (tc) 3 io pt21c pt28c ? l9t_d1 d31 ?? v ss v ss v ss ?? e21 1 (tc) 3 io pt21a pt28a ?? a21 1 (tc) 3 io pt20d pt27d ? l10c_d0 b20 1 (tc) 3 io pt20c pt27c ? l10t_d0 a11 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? a20 1 (tc) 3 io pt20a pt27a ?? e20 1 (tc) 4 io pt19d pt26d ? l11c_d0
100 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair d19 1 (tc) 4 io pt19c pt26c ? l11t_d0 c19 1 (tc) 4 io pt19b pt25d ? l12c_a0 b19 1 (tc) 4 io pt19a pt25c ? l12t_a0 n3 ?? v ss v ss v ss ?? e19 1 (tc) 4 io pt18d pt24d ? l13c_d0 d18 1 (tc) 4 io pt18c pt24c vref_1_04 l13t_d0 a17 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? b18 1 (tc) 4 io pt18b pt24b ? l14c_a0 c18 1 (tc) 4 io pt18a pt24a ? l14t_a0 b17 1 (tc) 5 io pt17d pt23d ptck1c l15c_a0 c17 1 (tc) 5 io pt17c pt23c ptck1t l15t_a0 n13 ?? v ss v ss v ss ?? a16 1 (tc) 5 io pt17b pt23b ? l16c_d2 d17 1 (tc) 5 io pt17a pt23a ? l16t_d2 b16 1 (tc) 5 io pt16d pt22d ptck0c l17c_a0 c16 1 (tc) 5 io pt16c pt22c ptck0t l17t_a0 d16 1 (tc) 5 io pt16a pt22a ?? e18 1 (tc) 5 io pt15d pt21d vref_1_05 l18c_d3 a15 1 (tc) 5 io pt15c pt21c ? l18t_d3 a19 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? b15 1 (tc) 5 io pt15a pt21a ?? d15 1 (tc) 6 io pt14d pt20d ? l19c_d2 a14 1 (tc) 6 io pt14c pt20c ? l19t_d2 n14 ?? v ss v ss v ss ?? b14 1 (tc) 6 io pt14a pt20a ?? e17 1 (tc) 6 io pt13d pt19d ? l20c_d2 c14 1 (tc) 6 io pt13c pt19c vref_1_06 l20t_d2 d14 1 (tc) 6 io pt13a pt19a ?? n15 ?? v ss v ss v ss ?? e16 0 (tl) 1 io pt11d pt18d mpi_rtry_n l1c_d3 a13 0 (tl) 1 io pt11c pt18c mpi_ack_n l1t_d3 b13 0 (tl) 1 io pt11b pt17d ? l2c_d0 a12 0 (tl) 1 io pt11a pt17c vref_0_01 l2t_d0 b12 0 (tl) 1 io pt10d pt16d m0 l3c_d1 d13 0 (tl) 1 io pt10c pt16c m1 l3t_d1 a34 ?? v ss v ss v ss ?? e15 0 (tl) 2 io pt10b pt15d mpi_clk l4c_d3 b11 0 (tl) 2 io pt10a pt15c a21/mpi_burst_n l4t_d3 a10 0 (tl) 2 io pt9d pt14d m2 l5c_d3 e14 0 (tl) 2 io pt9c pt14c m3 l5t_d3 a3 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? d12 0 (tl) 2 io pt9b pt13d vref_0_02 l6c_d0
agere systems inc. 101 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair c11 0 (tl) 2 io pt9a pt13c mpi_tea_n l6t_d0 b10 0 (tl) 3 io pt8d pt12d ? l7c_d0 a9 0 (tl) 3 io pt8c pt12c ? l7t_d0 c10 0 (tl) 3 io pt8b pt11d vref_0_03 l8c_d0 b9 0 (tl) 3 io pt8a pt11c ? l8t_d0 a8 0 (tl) 3 io pt7d pt10d d0 l9c_d2 d10 0 (tl) 3 io pt7c pt10c tms l9t_d2 b1 ?? v ss v ss v ss ?? c9 0 (tl) 4 io pt7b pt9d a20/mpi_bdip_n l10c_d0 b8 0 (tl) 4 io pt7a pt9c a19/mpi_tsz1 l10t_d0 a7 0 (tl) 4 io pt6d pt8d a18/mpi_tsz0 l11c_d4 e12 0 (tl) 4 io pt6c pt8c d3 l11t_d4 b3 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? d9 0 (tl) 4 io pt6b pt7d vref_0_04 l12c_d0 c8 0 (tl) 4 io pt6a pt7c ? l12t_d0 e11 0 (tl) 5 io pt5d pt6d d1 l13c_d3 b7 0 (tl) 5 io pt5c pt6c d2 l13t_d3 b2 ?? v ss v ss v ss ?? a6 0 (tl) 5 io pt5b pt5d ? l14c_d2 d8 0 (tl) 5 io pt5a pt5c vref_0_05 l14t_d2 c7 0 (tl) 5 io pt4d pt4d tdi l15c_d1 a5 0 (tl) 5 io pt4c pt4c tck l15t_d1 c1 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? e10 0 (tl) 5 io pt4b pt4b ? l16c_d2 d7 0 (tl) 5 io pt4a pt4a ? l16t_d2 a4 0 (tl) 6 io pt3d pt3d ? l17c_d4 e9 0 (tl) 6 io pt3c pt3c vref_0_06 l17t_d4 b33 ?? v ss v ss v ss ?? b6 0 (tl) 6 io pt3b pt3b ? l18c_a0 c6 0 (tl) 6 io pt3a pt3a ? l18t_a0 b5 0 (tl) 6 io pt2d pt2d pll_ck1c/ppll l19c_d1 d6 0 (tl) 6 io pt2c pt2c pll_ck1t/ppll l19t_d1 c2 0 (tl) ? v dd io0 v dd io0 v dd io0 ?? c5 0 (tl) 6 io pt2b pt2b ? l20c_d0 b4 0 (tl) 6 io pt2a pt2a ? l20t_d0 e8 ?? o pcfg_mpi_irq pcfg_mpi_irq cfg_irq_n/mpi_irq_n ? e7 ?? io pcclk pcclk cclk ? d5 ?? io pdone pdone done ? e6 ?? v dd 33 v dd 33 v dd 33 ?? b34 ?? v ss v ss v ss ?? a24 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? am23 5 (bc) ? v dd io5 v dd io5 v dd io5 ??
102 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair ap1 ?? v ss v ss v ss ?? k4 0 (tl) 10 io unused pl11a ?? m5 0 (tl) 10 io unused pl13a ?? r5 7 (cl) 3 io unused pl20a ?? t5 7 (cl) 3 io unused pl21a ?? w4 7 (cl) 5 io unused pl27a ?? aa2 7 (cl) 6 io unused pl28a ?? y4 7 (cl) 6 io unused pl29a ?? ac4 7 (cl) 8 io unused pl35a ?? ad5 7 (cl) 8 io unused pl37a ?? ag1 6 (bl) 1 io unused pl38a ?? ak10 6 (bl) 7 io unused pb9a ?? ak11 6 (bl) 7 io unused pb10a ?? am9 6 (bl) 8 io unused pb11a ?? an9 6 (bl) 8 io unused pb12a ?? am14 6 (bl) 11 io unused pb19a ?? an14 6 (bl) 11 io unused pb20a ?? d11 0 (tl) 3 io unused pt12a ?? e13 0 (tl) 3 io unused pt11a ?? ap4 6 (bl) 5 io unused pb3a ?? y3 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? ac3 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? ad1 7 (cl) ? v dd io7 v dd io7 v dd io7 ?? ap11 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? ap17 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? ap19 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? ap24 5 (bc) ? v dd io5 v dd io5 v dd io5 ?? c12 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? c15 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? c20 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? c23 1 (tc) ? v dd io1 v dd io1 v dd io1 ?? w22 ?? v dd 15 v dd 15 v dd 15 ?? y16 ?? v dd 15 v dd 15 v dd 15 ?? v22 ?? v dd 15 v dd 15 v dd 15 ?? u22 ?? v dd 15 v dd 15 v dd 15 ?? t22 ?? v dd 15 v dd 15 v dd 15 ?? p17 ?? v dd 15 v dd 15 v dd 15 ?? p18 ?? v dd 15 v dd 15 v dd 15 ?? n16 ?? v dd 15 v dd 15 v dd 15 ?? n17 ?? v dd 15 v dd 15 v dd 15 ?? n18 ?? v dd 15 v dd 15 v dd 15 ?? n19 ?? v dd 15 v dd 15 v dd 15 ??
agere systems inc. 103 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair p16 ?? v dd 15 v dd 15 v dd 15 ?? p19 ?? v dd 15 v dd 15 v dd 15 ?? r16 ?? v dd 15 v dd 15 v dd 15 ?? r17 ?? v dd 15 v dd 15 v dd 15 ?? r18 ?? v dd 15 v dd 15 v dd 15 ?? r19 ?? v dd 15 v dd 15 v dd 15 ?? t13 ?? v dd 15 v dd 15 v dd 15 ?? t14 ?? v dd 15 v dd 15 v dd 15 ?? t15 ?? v dd 15 v dd 15 v dd 15 ?? t20 ?? v dd 15 v dd 15 v dd 15 ?? t21 ?? v dd 15 v dd 15 v dd 15 ?? u13 ?? v dd 15 v dd 15 v dd 15 ?? u14 ?? v dd 15 v dd 15 v dd 15 ?? u15 ?? v dd 15 v dd 15 v dd 15 ?? u20 ?? v dd 15 v dd 15 v dd 15 ?? u21 ?? v dd 15 v dd 15 v dd 15 ?? v13 ?? v dd 15 v dd 15 v dd 15 ?? v14 ?? v dd 15 v dd 15 v dd 15 ?? v15 ?? v dd 15 v dd 15 v dd 15 ?? v20 ?? v dd 15 v dd 15 v dd 15 ?? v21 ?? v dd 15 v dd 15 v dd 15 ?? w13 ?? v dd 15 v dd 15 v dd 15 ?? w14 ?? v dd 15 v dd 15 v dd 15 ?? w15 ?? v dd 15 v dd 15 v dd 15 ?? w20 ?? v dd 15 v dd 15 v dd 15 ?? w21 ?? v dd 15 v dd 15 v dd 15 ?? y17 ?? v dd 15 v dd 15 v dd 15 ?? y18 ?? v dd 15 v dd 15 v dd 15 ?? y19 ?? v dd 15 v dd 15 v dd 15 ?? aa16 ?? v dd 15 v dd 15 v dd 15 ?? aa17 ?? v dd 15 v dd 15 v dd 15 ?? aa18 ?? v dd 15 v dd 15 v dd 15 ?? aa19 ?? v dd 15 v dd 15 v dd 15 ?? ab16 ?? v dd 15 v dd 15 v dd 15 ?? ab17 ?? v dd 15 v dd 15 v dd 15 ?? ab18 ?? v dd 15 v dd 15 v dd 15 ?? c3 ?? v ss v ss v ss ?? c13 ?? v ss v ss v ss ?? ap2 ?? v ss v ss v ss ?? ap18 ?? v ss v ss v ss ?? ap33 ?? v ss v ss v ss ?? ap34 ?? v ss v ss v ss ??
104 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc pin information (continued) table 34. ort8850l and ort8850h 680-pin pbgam pinout (continued) bm680 v dd io bank vref group i/o ort8850l ort8850h additional function pair aa20 ?? v ss v ss v ss ?? aa21 ?? v ss v ss v ss ?? aa22 ?? v ss v ss v ss ?? n21 ?? v ss v ss v ss ?? n22 ?? v ss v ss v ss ?? ab3 ?? v ss v ss v ss ?? ab19 ?? v dd 15 v dd 15 v dd 15 ?? n20 ?? v ss v ss v ss ??
agere systems inc. 105 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc package thermal characteristics summary there are three thermal parameters that are in com- mon use: ja , jc, and jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.). where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chip ? s heater resistor, the chip ? s temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is expressed in units of c/watt. jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is gener- ally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of c/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water- cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of c/w. jb this is the thermal resistance from junction to board ( jl ). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of c/w and that this parameter and the way it is mea- sured are still in jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpsc can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ja ) table 35 lists the thermal characteristics for all pack- ages used with the orca ort8850 series of fpscs. ja t j t a ? q ------------------- - = jc t j t c ? q -------------------- = jc t j t c ? q -------------------- = jb t j t b ? q ------------------- - =
106 106 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc package thermal characteristics table 35 . orca ort8850 plastic package thermal guidelines * the 680-pin pbgam package includes 2 oz copper plates. package coplanarity the coplanarity limits of the agere packages are as fol- lows: pbgam: 8.0 mils pbga: 8.0 mils package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 36 lists eight parasit- ics associated with the orca packages. these para- sitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capaci- tance of the lead to the nearest neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. resistance values are in m ?. the parasitic values in table 36 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer ? s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. package ja ( c/w) t = 70 c max, t j = 125 c max, 0 fpm (w) 0 fpm 200 fpm 500 fpm 352-pin pbga 19.0 16.0 15.0 2.90 680-pin pbgam * 13.4 11.5 10.5 4.10 table 36. orca ort8850 package parasitics 5-3862(c)r2 figure 25. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 352-pin pbga 5.0 2.0 220 1.5 1.5 1.5 7.0 ? 12.0 3.0 ? 6.0 680-pin pbgam 3.8 1.3 250 1.0 1.0 0.3 2.8 ? 5.0 0.5 ? 1.0 pad n board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl circuit
agere systems inc. 107 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc package outline diagrams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tol- erance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
108 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc package outline drawings 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 ? 0.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 ? 0.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below)
agere systems inc. 109 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 ? 0.00 35.00 30.00 + 0.70 ? 0.00 identifier zone 2.51 max 0.61 0.08
110 agere systems inc. data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc hardware ordering information 5-6435(f)p table 37. device type options table 38. temperature options table 39. package type options table 40 . orca fpsc package matrix (speed grades) device parameter value ort8850l voltage 1.5 v core. 3.3 v/2.5 v i/o. package 680-pin pbgam. 352-pin pbga. (four channels with redundancy only.) ort8850h voltage 1.5 v core. 3.3 v/2.5 v i/o. package 680-pin pbgam. symbol description temperature (blank) industrial ? 40 c to +85 c symbol description bm plastic ball grid array, multilayer ba plastic ball grid array device package 680-pin pbgam 352-pin pbga bm680 ba352 ort8850l ? 1, ? 2, ? 3 ? 1, ? 2, ? 3 ort8850h ? 1, ? 2, ? 3 ? device type package type ort8850(l)(h) bm number of pins temperature range 680 -2 speed grade
agere systems inc. 111 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc software ordering information implementing a design in an ort8850h/l requires the orca foundry development system and an ort8850 fpsc desgin kit. for ordering information, please visit: http://www.agere.com/netcom/ipkits/ort8850/
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. orca is a registered trademark of agere systems inc. foundry is a trademark of xilinx. copyright ? 2001 agere systems inc. all rights reserved august 2001 ds01-198ncip (replaces ds01-094ncip) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com or for fpgas/fpscs: http://www.agere.com/orca e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 data sheet august 2001 eight-channel x 850 mbits/s backplane transceiver orca ort8850 fpsc motorola is a registered trademark and rapidio is a trademark of motorola, inc. eia is a registered trademark of electronic industries association. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. pal is a trademark of advanced micro devices, inc. powerpc is a registered trademark of international business machines, corporation. amba is a trademark and arm is a registered trademark of advanced risc machines limited. synopsys smart model is a registed trademark of synopsys, inc.

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